Static memory cell
AssigneeSharp Kabushiki Kaisha
InventorAtsushi Semi
Life of this patent
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Abstract
A static memory cell is connected to a first bit line and a second bit line, and includes the following: a first inverter section having a first input and a first output; a second inverter section having a second input connected to a first output through a first node, and a second output connected to the first input through a second node; a first switching section for allowing or not allowing conduction between the first bit line and the first node; a first capacitor arranged between the second bit line and the first node; a second switching section for allowing or not allowing conduction between the second bit line and the second node; and a second capacitor arranged between the first bit line and the second node.
Claims5
A static memory cell connected to a first bit line and a second bit line, comprising:
- a first inverter means including a first input terminal and a first output terminal;
- a second inverter means including a second input terminal connected to a first output terminal through a first node, and a second output terminal connected to the first input terminal through a second node;
- a first switching means for allowing or not allowing conduction between the first bit line and the first node;
- a first capacitor connected between the second bit line and the first node;
- a second switching means for allowing or not allowing conduction between the second bit line and the second node;
- and
- a second capacitor connected between the first bit line and the second node.
Dependencies are inferred from the claim text.