Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of first memory cell arrays which share first bit lines with each other, each of said plural first memory cell arrays having a first word line and a sense line, and having functions of storing information on said first bit lines at assertion of said first word line and of asserting said sense line when the stored information conforms to other information on said first bit lines;
• a plurality of second memory cell arrays which share second bit lines and third bit lines with each other, said second and third bit lines being separated from each other, each of said plural second memory cell arrays sharing said first word line with one of said plural first memory cell arrays so as to compose one entry, each of said plural second memory cell arrays having a second word line and having functions of storing information on said second bit lines at assertion of said first word line and of outputting the stored information onto said third bit lines at assertion of said second word line;
• a plurality of sense circuits intervening between said plural first memory cell arrays and said plural second memory cell arrays, each of said plural sense circuits having a function of asserting said second word line of one of said plural second memory cell arrays at assertion of said sense line of corresponding one of said plural first memory cell arrays in the same entry;
• and
• an entry selecting circuit for asserting one of said first word lines.