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US 5,327,239 AGranted
Video data splitting circuit
AssigneeSamsung Electronics Co., Ltd.
InventorKi B. Kim
Life of this patent
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Abstract
A video data splitting circuit is disclosed, and the circuit includes a control part and a signal holding and outputting part. The control part includes a sequential address generator, a random address generator, a first selector, an inverter, and a second selector. The signal holding and outputting part includes a first latch, a first memory, a second latch, a third latch, a second memory and a third selector. According to the present invention, the noises added to the transmitting signals are dispersed, so that the final picture at the receiving end should not be affected by the noises.
Claims20
A video data splitting circuit for removing noise during the transmission of video signals, comprising:
- control means for sequentially generating sequential address signals and pseudo-random address signals on the basis of a period of a horizontal synchronizing signal after being synchronized with a clock signal, for alternately selecting said sequential address signal and said pseudo-random address signal in accordance with first and second complementary control signals to simultaneously produce first and second address signals;
- and
- signal holding and outputting means coupled to receive video signals, for sequentially writing video signals onto a memory to provide stored video signals and for randomly reading and outputting stored video signals in a scrambled form in accordance with said first and second address signals and said first and second complementary control signals.
A video data splitting circuit for removing transmission noise, comprising:
- control means coupled to receive a clock signal and a horizontal synchronizing signal, for generating sequential address signals and pseudo-random address signals in synchronization with said clock signal based on a period of said horizontal synchronizing signal, for receiving a first control signal for inverting said first control signal to generate a second control signal, and for sequentially generating first and second address signals from said address signals and said pseudo-random address signals in response to said first and second control signals;
- and
- noise reducing means coupled to receive video signals for sequentially writing said video signals in synchronization with said clock signal based on the period of said horizontal synchronizing signal into designated addresses in accordance to said first and second control signals and said first and second address signals, and for randomly reading said video signals from said designated addresses to generate said video signals in a scrambled format.
A method for minimizing transmission noise in video signals, comprising the steps of:
- receiving a clock signal and a horizontal synchronizing signal to generate sequential address signals in synchronization with said clock signal based on a period of said horizontal synchronizing signal;
- receiving said clock signal to randomly generate pseudo-random address signals in synchronization with said horizontal synchronizing signal;
- receiving a first control signal and inverting said first control signal to generate a second control signal;
- selecting said sequential address signals and said pseudo-random address signals in response to said first control signal to generate a first address signal;
- selecting said sequential address signals and said pseudo-random address signals in response to said second control signal to generate a second address signal;
- receiving video signals and latching said video signals to provide latch video signals;
- receiving said first address signal and sequentially writing said latch video signals into first designated addresses of a memory in accordance with said first control signal when said first address signal is sequentially generated, and for randomly reading said latch video signals from said designated addresses in accordance with said first control signal when said first address signal is randomly generated to provide first read signals;
- latching said first read signals to perform timing corrections and wave pattern corrections for providing first intermediate signals;
- receiving said second address signal and sequentially writing said latch video signals into second designated addresses of said memory in accordance with said second control signal when said second address signal is sequentially generated, and randomly reading said latch video signals from said second designated addresses in accordance with said second control when said second address signal is randomly generated to provide second read signals;
- latching said second read signals to perform timing corrections and wave pattern corrections to provide second intermediate signals;
- and
- selecting between said first intermediate signals and said second intermediate signals to provide video signals in said scrambled format.
9 more elements
A video data splitting circuit, comprising:
- means for receiving video signals;
- control means for controlling pseudo-random and sequential generation of first and second addresses signals in dependence upon synchronizing signals;
- first memory means having first designated addresses, for sequential writing said video signals into said first designated addresses and for randomly reading said video signals from said first designated addresses in dependence upon said first address signal to generate first reproduced video signals;
- second memory means having second designated addresses, for sequential writing said video signals into said second designated addresses and for randomly reading said video signals from said second designated addresses in dependence upon said second address signal to generate second reproduced video signals;
- and
- means for enabling transmission of one of said first and second reproduced video signals as video signals of a scrambled wave pattern.
3 more elements
A video data splitting circuit, comprising:
- means for receiving video signals of a standard wave pattern;
- first generating means for sequentially generating sequential address signals in dependence upon synchronizing signals and clock signals;
- second generating means for pseudo-randomly generating pseudo-random address signals in dependence upon said synchronizing signals and said clock signals;
- selecting means for selecting said sequential address signals and said pseudo-random address signals to produce first and second address signals;
- memory means for sequential writing said video signals into a plurality of addresses and for randomly reading said video signals from said plurality of addresses in dependence upon said first and second address signals to produce first and second reproduced video signals;
- and
- means for enabling transmission of one of said first and second reproduced video signals as video signals of a scrambled wave pattern.
4 more elements
A method for minimizing transmission noise of video signals, comprising the steps of:
- receiving video signals of a standard wave pattern;
- sequentially generating sequential address signals and pseudo-randomly generating pseudo-random address signals in dependence upon synchronizing signals and and clock signals;
- selecting said sequential address signals and said psuedo-random address signals to generate first and second address signals;
- sequential writing said video signals into a plurality of addresses of a memory and for randomly reading said video signals from said plurality of addresses of said memory in dependence upon said first and second address signals to generate first and second reproduced video signals;
- and
- enabling transmission of one of said first and second reproduced video signals as video signals of a scrambled wave pattern.
3 more elements
Dependencies are inferred from the claim text.