Circuit for detecting odd and even fields of a video signal

Abstract

A circuit for detecting odd and even numbered fields of a video signal includes a first counter circuit for counting a clock pulse input to detect a vertical synchronous pulse interval of the video signal, a second counter circuit for counting the clock pulse upon detection of the vertical synchronous pulse interval to generate a window signal and a counting signal having a predetermined pulse width, and an output circuit responsive to horizontal synchronous pulses and the window signal to generate a first logic state remaining for a next vertical synchronous pulse interval or generate a second logic state remaining for the next vertical synchronous pulse interval, whereby the output circuit maintains the first logic state for the odd field and the second logic state for the even field.

Dependencies are inferred from the claim text.