Series-parallel A-D converter
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsShiro Hosotani, Takahiro Miki
Life of this patent
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsShiro Hosotani, Takahiro Miki
Estimating the term…
Low-order reference potentials including high-order reference potentials (VRT, VRB, VC0 to VC6) generated from a ladder resistor and potentials (V(i, j) (i=0 to 7, j=0 to 6)) are applied to potential lines, respectively, to be transmitted by various switches to analog bus lines (FR0a to FR14a) or analog bus lines (FR0b FR14b). The low-order reference potentials are applied to the analog bus lines (FR0b to FR14b) when it is judged that a sample signal potential falls in voltage zones (Z0 to Z3) as a result of comparison with the high-order reference potentials and are applied to the analog bus lines (FR0a to FR14a) when it is judged that the sample signal potential falls in voltage zones (Z4 to Z7). This provides for reduction in the number of switches connected to each analog bus line and in parasitic capacitance, so that a settling time of the low-order reference potentials is shortened. High-speed operation of a series-parallel A-D converter is achieved.
A series-parallel A-D converter comprising
A series-parallel A-D converter comprising
Dependencies are inferred from the claim text.