Back to results
US 5,327,128 AGranted
Compact glitchless M of N decoder circuit for digital to analog converters
AssigneeCirrus Logic, Inc.
InventorMan S. Lee
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeCirrus Logic, Inc.
InventorMan S. Lee
Estimating the term…
An M of N decoder circuit includes N output terminals, log.sub.2 (n+1) logic input terminals, two voltage input terminals, and (N+1)log.sub.2 (N+1) pass transistors, each having a gate connected to one of the logic input terminals, a source connected to one of a voltage input terminal and an output terminal, and a drain connected to one of said output terminals, each of the pass transistors for passing a voltage signal from source to drain when the gate has applied to it one logic level and for not passing said voltage signal when the gate has applied to a different logic level. More particularly, half of the pass transistors are of one conduction type and half of the pass transistors are of an opposite conduction type. The gates of N+1 pass transistors are connected to each of the log.sub.2 (M+1) input terminals. For i =0 to log.sub.2 (N+1)-1, pass transistors of one conduction type whose gates are connected to an i-th input terminal are connected in groups of 2.sup.i, and pass transistors of the opposite conduction type whose gates are connect to the i-th input terminal are also connected in groups of 2.sup.i.
An M-of-N decoder circuit comprising:
A decoder circuit, comprising:
A decoder circuit, comprising:
Dependencies are inferred from the claim text.