Apparatus for and method of parallel justifying and dejustifying data in accordance with a predetermined mapping

A de-justifier for performing the parallel de-justification of data from a predetermined mapping, said de-justifier including:

• an input bus for selectively communicating a plurality of information bits to said de-justifier;
• control means responsive to a control signal indicative of said mapping for providing a remainder signal;
• a shifter communicating with said input bus and being responsive to said remainder signal during a first cycle for arranging said information bits in a desired significant bit position on said input bus;
• a first data path connecting said input bus to first inputs of a first multiplexer;
• a second data path connecting said input bus to second inputs of said first multiplexer;
• said first multiplexer being responsive to said remainder signal during a second cycle following said first cycle for communicating a predetermined number of said information bits from said first and second data paths to an output bus such that said information bits are extracted from said mapping and retained in sequence.

A method of performing parallel justification of data in accordance with a predetermined mapping, said method including:

• selectively communicating on an input bus a plurality of information bits to a justifier;
• providing a control signal indicative of said mapping to control means, the control means subsequently providing a remainder signal;
• communicating the information bits on said input bus to first inputs of a multiplexer via a first data path having a first shifter responsive to said remainder signal during a first cycle so a predetermined number of said information bits are shifted from said input bus into the least significant bit position or positions of said first data path;
• communicating the information bits on said input bus to second inputs of said multiplexer via a second data path having a second shifter responsive to said remainder signal during a second cycle following said first cycle so the remainder of the information bits are shifted from said input bus into the least significant bit position or positions of said second data path;
• and
• supplying said multiplexer with said remainder signal during a third cycle following said second cycle so said information bits are communicated from said first and second data paths to an output bus such that said mapping is followed and the sequence of said information bit is maintained.

A method of performing parallel de-justification of data from a predetermined mapping, said method including:

• selectively communicating on an input bus a plurality of information bits to a de-justifier;
• providing a control signal indicative of said mapping to control means, the control means subsequently providing a remainder signal;
• responding to said remainder signal during a first cycle so said information bits are arranged in a desired significant bit position on said input bus;
• communicating said information bits on said input bus to first inputs of a first multiplexer via a first data path;
• communicating said information bits on said input bus to second inputs of said first multiplexer via a second data path;
• providing said first multiplexer with said remainder signal during a second cycle following said first cycle so the predetermined number of said information bits are communicated from said first and second data paths to an output bus such that said information bits are extracted from said mapping and retained in sequence.