Programmable gain amplifier circuitry and method for biasing JFET gain switches thereof

Circuitry for reducing input offset error in a high speed programmable gain amplifier including an operational amplifier having a non-inverting input receiving a first input signal, a differential input stage having a common mode voltage conductor carrying a first signal level representative of the first input signal, a gain network coupled between an output and an inverting input of the operational amplifier, and a plurality of gain-switching JFETs coupling the gain network to the inverting input, the circuitry comprising in combination:

• (a) a buffer circuit;
• (b) means for applying the first signal level to an input of the buffer circuit, causing it to produce a second signal level;
• (c) means for coupling the second signal level to a gate of one of the gain-switching JFETs to couple a conductor of the gain switching network to the inverting input if a gain select input signal is at a first logic level;
• and
• (d) means for both isolating the gate of the one of the gain switching JFETs from the second signal level and applying a turn-off voltage to the gate of the one of the gain switching JFETs if the gain select input signal is at a second logic level.

Circuitry for reducing input offset error in a high speed programmable gain amplifier including a first operational amplifier having a non-inverting input receiving a first input signal, a differential input stage having a first common mode voltage conductor carrying a first signal representative of the first input signal, a second operational amplifier having a non-inverting input receiving a second input signal, a differential input stage having a second common mode voltage conductor carrying a second signal representative of the second input signal, a gain network coupled to outputs of the first and second operational amplifiers and inverting inputs of the first and second operational amplifiers, and a plurality of gain-switching JFETs coupling the gain network to the inverting inputs, the circuitry comprising in combination:

• (a) first and second buffer circuits;
• (b) means for applying the first signal to an input of the first buffer circuit, causing it to produce a third signal;
• (c) means for applying the second signal to an input of the second buffer circuit, causing it to produce a fourth signal;
• (d) means for coupling the third signal to a gate of a first gain-switching JFET to couple a first conductor of the gain switching network to the inverting input of the first operational amplifier if a gain select input signal is at a first logic level;
• (e) means for coupling the fourth signal to a gate of a second gain-switching JFET to couple a second conductor of the gain switching network to the inverting input of the second operational amplifier if a gain select input signal is at the first logic level;
• (f) means for both isolating the gate of the first gain switching JFET from the third signal and applying a first turnoff voltage to the gate of the first gain switching JFET if the gain select input signal is at a second logic level;
• and
• (g) means for both isolating the gate of the second gain switching JFET from the fourth signal and applying a second turn-off voltage to the gate of the second gain switching JFET if the gain select input signal is at the second logic level.

A method of biasing a gain switching JFET in a programmable gain amplifier including an operational amplifier having a non-inverting input receiving an input signal, a differential input stage having a common mode voltage conductor carrying a first signal representative of the first input signal, a gain network coupled between an output of the operational amplifier and an inverting input of the operational amplifier, the gain-switching JFET coupling the gain network to the inverting input, the method including the steps of:

• (a) applying the first signal to an input of a buffer circuit, causing it to produce a second signal;
• and
• (b) applying the second signal to a gate of the gain-switching JFET to couple a conductor of the gain switching network to the inverting input if a gain select input signal is at a first logic level, and
• (c) if the gain select signal is at a second logic level, both (1) isolating the gate of the gain switching JFET from the second signal, and (2) applying a turn-off voltage to the gate of the gain switching JFET.

A programmable gain amplifier comprising in combination:

• (a) a first operational amplifier having an inverting input and a non-inverting input, the non-inverting input receiving an input signal;
• (b) a buffer circuit having an input coupled to the inverting input and also having an output carrying an output signal representative of the input signal;
• (c) a gain network coupled between an output of the operational amplifier and the inverting input of the operational amplifier;
• (d) a group of gain-switching JFETs coupling the gain network to the inverting input of the operational amplifier;
• and
• (e) a first group of control circuit means, each coupled to the output of the buffer circuit, for selectively applying the output signal to a gate of one of the gain-switching JFETs of the group.