Gain control circuit

A gain control circuit, comprising:

• a current dividing type gain control unit including, first and second transistors having emitters connected to each other;
• a high frequency check means having one end connected to the collector of said first transistor and the other end connected to the collector of said second transistor for checking a high frequency signal current;
• an input terminal composed of the node where said emitters are connected to each other for causing an emitter direct current to be conducted therethrough and a signal current also to be input thereto;
• an output terminal composed of the node where the collector of one of said first and second transistors is connected to said high frequency check means for causing a collector direct current to be conducted therethrough and a signal current also to be output therefrom;
• and
• a means for changing the dividing ratio of the collector direct current to said first and second transistors, whereby gain is controlled by said dividing ratio;
• and
• a second current dividing type gain control unit composed of third and fourth transistors having emitters connected to the output terminal of said current dividing type gain control unit and the node where said emitters are connected to each other serves as an input terminal for causing an emitter direct current to be conducted therethrough and a signal current also to be input thereto.

A gain control circuit device, comprising:

• a first gain control circuit including:
• first and second transistors having emitters connected to each other and to an input terminal, collectors connected to a first output terminal, and bases connected to receive first and second gain control voltage signals, respectively, and
• a high frequency blocking element connected between the collector of one of the first and second transistors and the output terminal;
• and a second gain control circuit including:
• third and fourth transistors having emitters connected to each other and to the first output terminal, collectors connected to a power supply, and bases connected to receive third and fourth gain control voltage signals, respectively,
• a load resistor connected between the collector of one of the third and fourth transistors and the power supply, and
• a second output terminal located between the resistor and the collector of said one of said third and fourth transistors;
• wherein a gain of an output signal on the second output terminal is altered by varying one or more of the first, second, third and fourth gain control voltage signals.

A gain control circuit device, comprising:

• a first gain control circuit including:
• first and second transistors having emitters connected to each other and to a first input terminal, collectors connected to a first output terminal, and bases connected to receive first and second gain control voltage signals, respectively,
• third and fourth transistors having emitters connected to each other and to a second input terminal, collectors connected to a second output terminal, and bases connected to receive said second and first gain control voltage signals, respectively,
• a first high frequency blocking element connected between the collector of one of the first and second transistors and the first output terminal, and
• a second high frequency blocking element connected between the collector of one of the third and fourth transistors and the second output terminal;
• and a second gain control circuit including:
• fifth and sixth transistors having emitters connected to each other and to the first output terminal, collectors connected to a power supply, and bases connected to receive third ad fourth gain control voltage signals, respectively,
• seventh and eighth transistors having emitters connected to each other and to the second output terminal, collectors connected to said power supply, and bases connected to receive said fourth and third gain control voltage signals, respectively,
• a load resistor connected between the collector of one of the seventh and eighth transistors and the power supply, and
• a third output terminal located between the load resistor and the collector of said one of said seventh and eighth transistors;
• wherein a gain of an output signal on the third output terminal is altered by varying one or more of the first, second, third and fourth gain control voltage signals.