Field programmable antifuse device and programming method therefor
AssigneeQuickLogic Corporation
InventorWilliam D. Cox
Life of this patent
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AssigneeQuickLogic Corporation
InventorWilliam D. Cox
Estimating the term…
A method for reducing the resistance of a programming path through a programmable antifuse from a programming voltage to ground. A previously programmed helper antifuse connected somewhere along a two branch programming path is connected to either the programming voltage or to ground. As a result, a three branch programming path is established from the programming voltage to the antifuse to be programmed and from the antifuse to be programmed to ground. By adding the third branch to the programming path, the resistance of the programming path is reduced, thereby allowing a higher voltage to be dropped across the antifuse to be programmed during programming and thereby allowing increased current flow through the antifuse to be programmed during programming. In another embodiment, two or more helper antifuses are used to establish a four or more branch programming path having a still lower resistance from the programming voltage to ground. In yet another embodiment, the programming of antifuses occurs in two steps. First, multiple antifuses are partially programmed separately. Second, these partially programmed antifuses are connected together in series so that a programming current can flow through all of the partially programmed antifuses at once to complete programming of the multiple antifuses.
In a programmable device, a method for reducing a resistance between a first portion of an antifuse to be programmed and a conductor carrying a first programming voltage, comprising the steps of:
In a programmable device, a method for reducing a resistance between a first portion of an antifuse to be programmed and a conductor carrying a first programming voltage, comprising the steps of:
In a programmable device, a method for reducing a resistance between a first portion of an antifuse to be programmed and a conductor carrying a first programming voltage, comprising the steps of:
In a programmable device, a method for reducing a resistance between a first portion of an antifuse to be programmed and a conductor carrying a first programming voltage, comprising the steps of:
In a programmable device, a method for reducing a resistance between a first portion of an antifuse to be programmed and a conductor carrying a first programming voltage, comprising the steps of:
A method for at least partially programming a first antifuse, comprising the steps of:
A method of realizing a user-specific circuit in a field programmable gate array chip, said user-specific circuit receiving a plurality of off-chip input electrical signals during normal operation and outputting a plurality of off-chip output electrical signals based on said off-chip input electrical signals during normal operation, said user-specific circuit comprising a plurality of digital logic components and a plurality of interconnection nets, each of said nets of said userspecific circuit being switchable during normal operation to determine said off-chip output electrical signals based on said off-chip input electrical signals, comprising the step of:
A method of connecting a programming branch to a net of a user-specific circuit realized in a field programmable device, comprising the step of:
In a programmable device comprising:
In a programmable device, a method for reducing a resistance from an antifuse to be programmed to a first programming voltage, comprising the steps of:
Dependencies are inferred from the claim text.