Thin, dielectrically isolated island resident transistor structure having low collector resistance

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of a first conductivity type;
• a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said first conductivity type of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of said first conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of said second conductivity type, contiguous with and having a depth greater than that of said first semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, said first, second and third bias voltages being such that a portion of said island region which extends beneath said first semiconductor region and separates a bottom portion of said first semiconductor region from a bottom portion of said island region is depleted of carriers prior to the occurrence of a breakdown voltage field between said island region and said first semiconductor region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of a first conductivity type;
• a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said first conductivity type of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region than at the bottom of said island region;
• a second semiconductor region of said first conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of said first conductivity type and an impurity concentration greater than that of said island region formed in a second surface portion of said island region, spaced apart from said first surface portion thereof by a third surface portion of said island region therebetween;
• a fourth semiconductor region of said second conductivity type, disposed in said third surface portion of said island region such that a surface path from said first semiconductor region to said third semiconductor region through a surface portion of said island region is interrupted by semiconductor material of said fourth semiconductor region, said fourth semiconductor region having a depth greater than a depth of said second semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first and fourth semiconductor regions, said first, second and third bias voltages being such that a portion of said island region which extends beneath said fourth semiconductor region and separates a bottom portion of said fourth semiconductor region from a bottom portion of said island region is depleted of carriers prior to the occurrence of a breakdown voltage field between said island region and said first semiconductor region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of a first conductivity type;
• a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said first conductivity type of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is greater at an interface with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of said first conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of said conductivity type and an impurity concentration greater than that of said island region formed in a second surface portion of said island region, spaced apart from said first surface portion thereof by a third surface portion of said island region therebetween;
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, said first, second and third bias voltages being such that a portion of said island region which extends beneath said first semiconductor region and separates a bottom portion of said first semiconductor region from a bottom portion of said island region is depleted of carriers prior to the occurrence of a breakdown voltage field between said island region and said first semiconductor region;
• an insulator layer formed on said third surface portion of said island region and overlapping the first and second surface portions of said island region;
• and
• a conductive layer formed on said insulator layer.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of N conductivity type;
• a first semiconductor region of P conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of N conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of P conductivity type, contiguous with and having a depth greater than that of said first semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, and wherein said first bias voltage is more negative than said second bias voltage.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of P conductivity type;
• a first semiconductor region of N conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of P conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of N conductivity type, contiguous with and having a depth greater than that of said first semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, and wherein said first bias is more positive than said second bias voltage.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of N conductivity type;
• a first semiconductor region of P conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region than at the bottom of said island region;
• a second semiconductor region of N conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of N conductivity type and an impurity concentration greater than that of said island region formed in a second surface portion of said island region, spaced apart from said first surface portion thereof by a third surface portion of said island region therebetween;
• a fourth semiconductor region of P conductivity type, disposed in said third surface portion of said island region such that a surface path from said first semiconductor region to said third semiconductor region through a surface portion of said island region is interrupted by semiconductor material of said fourth semiconductor region, said fourth semiconductor region having a depth greater than a depth of said second semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first and fourth semiconductor regions, and wherein said first bias voltage is more negative than said second bias voltage.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of P conductivity type;
• a first semiconductor region of N conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region than at the bottom of said island region;
• a second semiconductor region of P conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of P conductivity type and an impurity concentration greater than that of said island region formed in a second surface portion of said island region, spaced apart from said first surface portion thereof by a third surface portion of said island therebetween;
• a fourth semiconductor region of N conductivity type, disposed in said third surface portion of said island region such that a surface path from said first semiconductor region to said third semiconductor region through a surface portion of said island region is interrupted by semiconductor material of said fourth semiconductor region, said fourth semiconductor region having a depth greater than a depth of said second semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first and fourth semiconductor regions, and wherein said first bias voltage is more positive than said second bias voltage.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of a first conductivity type;
• a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said first conductivity type of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is greater at an interface with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of said first conductivity type, formed in a first surface portion of said first semiconductor region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, said first, second and third bias voltages being such that a portion of said island region which extends beneath said first semiconductor region and separates a bottom portion of said first semiconductor region from a bottom portion of said island region is depleted of carriers prior to the occurrence of a breakdown voltage field between said island region and said first semiconductor region,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of a first conductivity type;
• a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said first conductivity type of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region that at said bottom portion of said island region;
• a second semiconductor region of said first conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of said second conductivity type, contiguous with and having a depth greater than that of said first semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, said first, second and third bias voltages being such that a portion of said island region which extends beneath said first semiconductor region and separates a bottom portion of said first semiconductor region from a bottom portion of said island region is depleted of carriers prior to the occurrence of a breakdown voltage field between said island region and said first semiconductor region,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of a first conductivity type;
• a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said first conductivity type of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region than at the bottom of said island region;
• a second semiconductor region of said first conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of said first conductivity type and an impurity concentration greater than that of said island region formed in a second surface portion of said island region, spaced apart from said first surface portion thereof by a third surface portion of said island therebetween;
• a fourth semiconductor region of said second conductivity type, disposed in said third surface portion of said island region such that a surface path from said first semiconductor region to said third semiconductor region through a surface portion of said island region is interrupted by semiconductor material of said fourth semiconductor region, said fourth semiconductor region having a depth greater than a depth of said second semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first and fourth semiconductor regions, said first, second and third bias voltages being such that a portion of said island region which extends beneath said fourth semiconductor region and separates a bottom portion of said fourth semiconductor region from a bottom portion of said island region is depleted of carriers prior to the occurrence of a breakdown voltage field between said island region and said first semiconductor region,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of a first conductivity type;
• a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said first conductivity type of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is greater at an interface with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of said first conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of said first conductivity type and an impurity concentration greater than that of said island region formed in a second surface portion of said island region, spaced apart from said first surface portion thereof by a third surface portion of said island region therebetween;
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, said first, second and third bias voltages being such that a portion of said island region which extends beneath said first semiconductor region and separates a bottom portion of said first semiconductor region from a bottom portion of said island region is depleted of carriers prior to the occurrence of a breakdown voltage field between said island region and said first semiconductor region;
• an insulator layer formed on said third surface portion of said island region and overlapping the first and second surface portions of said island region;
• and
• a conductive layer formed on said insulator layer,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of N conductivity type;
• a first semiconductor region of P conductivity type, formed in a first surface portion of said island region, such that N type semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is greater at an interface with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of N conductivity type, formed in a first surface portion of said first semiconductor region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, and wherein said first bias voltage is more negative than said second bias voltage,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of P conductivity type;
• a first semiconductor region of N conductivity type, formed in a first surface portion of said island region, such that P type semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is greater at an interface with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of P conductivity type, formed in a first surface portion of said first semiconductor region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, and wherein said first bias voltage is more positive than said second bias voltage,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of N conductivity type;
• a first semiconductor region of P conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of N conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of P conductivity type, contiguous with and having a depth greater than that of said first semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, and wherein said first bias voltage is more negative than said second bias voltage,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of P conductivity type;
• a first semiconductor region of N conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of P conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of N conductivity type, contiguous with and having a depth greater than that of said first semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, and wherein said first bias voltage is more positive than said second bias voltage,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of N conductivity type;
• a first semiconductor region of P conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region than at the bottom of said island region;
• a second semiconductor region of N conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of N conductivity type and an impurity concentration greater than that of said island region formed in a second surface portion of said island region, spaced apart from said first surface portion thereof by a third surface portion of said island region therebetween;
• a fourth semiconductor region of P conductivity type, disposed in said third surface portion of said island region such that a surface path from said first semiconductor region to said third semiconductor region through a surface portion of said island region is interrupted by semiconductor material of said fourth semiconductor region, said fourth semiconductor region having a depth greater than a depth of said second semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first and fourth semiconductor regions, and wherein said first bias voltage is more negative than said second bias voltage,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of P conductivity type;
• a first semiconductor region of N conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is higher at a portion thereof contiguous with said first semiconductor region than at the bottom of said island region;
• a second semiconductor region of P conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of P conductivity type and an impurity concentration greater than that of said island region formed in a second surface portion of said island region, spaced apart from said first surface portion thereof by a third surface portion of said island region therebetween;
• a fourth semiconductor region of N conductivity type, disposed in said third surface portion of said island region such that a surface path from said first semiconductor region to said third semiconductor region through a surface portion of said island region is interrupted by semiconductor material of said fourth semiconductor region, said fourth semiconductor region having a depth greater than a depth of said second semiconductor island region;
• and
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first and fourth semiconductor regions, and wherein said first bias voltage is more positive than said second bias voltage,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of N conductivity type;
• a first semiconductor region of P conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is greater at an interface with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of N conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of N conductivity type and an impurity concentration greater than that of said island region formed in a second surface portion of said island region, spaced apart from said first surface portion thereof by a third surface portion of said island region therebetween;
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, and wherein said first bias voltage is more negative than said second bias voltage;
• an insulator layer formed on said third surface portion of said island region and overlapping the first and second surface portions of said island region;
• and
• a conductive layer formed on said insulator layer,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A semiconductor device comprising:

• a semiconductor substrate having a dielectrically isolated island region of semiconductor material of P conductivity type;
• a first semiconductor region of N conductivity type, formed in a first surface portion of said island region, such that semiconductor material of said island region extends beneath said first semiconductor region and thereby separates a bottom portion of said first semiconductor region from a bottom portion of said island region, and wherein said island region has an impurity concentration which is greater at an interface with said first semiconductor region than at said bottom portion of said island region;
• a second semiconductor region of P conductivity type, formed in a first surface portion of said first semiconductor region;
• a third semiconductor region of P conductivity type and an impurity concentration greater than that of said island region formed in a second surface portion of said island region, spaced apart from said first surface portion thereof by a third surface portion of said island region therebetween;
• wherein said substrate is biased at a first bias voltage, said island region is biased at a second bias voltage, and said first semiconductor region is biased at a third bias voltage, said second and third bias voltages establishing a reverse bias voltage differential between said island region and said first semiconductor region, and wherein said first bias voltage is more positive than said second bias voltage;
• an insulator layer formed on said third surface portion of said island region and overlapping the first and second surface portions of said island region;
• and
• a conductive layer formed on said insulator layer,
• further including a channel of material dielectrically isolated from said substrate and said island region, disposed adjacent to said island region.

A bipolar transistor device comprising:

• a semiconductor substrate having a dielectrically isolated collector island region;
• a base region formed in a first surface portion of said collector region, such that said collector region extends beneath said base and separates a bottom portion of said base region from a bottom portion of said collector island region, and wherein said collector island region has an impurity concentration which is greater at an interface with said base semiconductor region than at said bottom portion of said collector island region;
• an emitter region formed in a first surface portion of said base region;
• a first bias potential applied to said substrate;
• and
• a second bias potential applied to said collector island region;
• and
• wherein said first and second bias potentials have respective values such that the value of BVCEO of the bipolar transistor is approximately equal to what its value would be absent the impurity concentration of said collector island region being higher at said interface with said base region than at the bottom portion of said collector island region,
• further including a channel of material dielectrically isolated from said semiconductor substrate and said collector island region, disposed adjacent to said collector island region.