Non-volatile semiconductor memory device and manufacturing method thereof

A semiconductor memory device, comprising:

• a plurality of non-volatile memory cells each comprised of a storage transistor and a select transistor having respective gate structures separated by a short distance from each other;
• wherein said gate structure of each said storage transistor includes:
• a first layer comprised of a tunneling oxide film and a contiguous first insulating film formed on a surface of a semiconductor substrate;
• a floating gate comprised of a first conductive layer formed on said first insulating layer;
• an second insulating layer formed on said floating gate;
• and,
• a control gate comprised of a second conductive layer formed on said second insulating layer;
• wherein said gate structure of each said select transistor includes:
• a first insulating layer formed on said surface of said semiconductor substrate;
• a first conductive layer formed on said first insulating layer;
• a second insulating layer formed on said first conductive layer;
• and,
• a second conductive layer formed on said second insulating layer;
• wherein, in each said non-volatile memory cell, a flank portion of said first conductive layer of said select transistor extends beyond said second insulating layer and said second conductive layer towards said gate structure of said storage transistor;
• and,
• wherein each of said non-volatile memory cells further includes:
• a first diffusion region formed in said surface of said semiconductor substrate between said respective gate structures of said select transistor and said storage transistor and at least partially beneath said tunneling oxide film of said storage transistor;
• a second diffusion region formed in said surface of said semiconductor substrate adjacent a side of said gate structure of said select transistor opposite from said gate structure of said storage transistor;
• a third diffusion region formed in said surface of said semiconductor substrate adjacent a side of said gate structure of said storage transistor opposite from said gate structure of said select transistor;
• a device insulating layer formed on said surface of said semiconductor substrate and said respective gate structures of said select and storage transistors;
• a first contact hole formed in said device insulating layer to leave a marginal edge portion of an upper surface of said second conductive layer of said select transistor and said flank portion of said first conductive layer of said select transistor uncovered by said device insulating layer;
• and,
• a conductive material disposed in said first contact hole to thereby form a butted contact electrically coupling said first and second conductive layers of said select transistor.