Charge skimming and variable integration time in focal plane arrays
AssigneeLoral Fairchild Corporation
InventorMichael J. McNutt
Life of this patent
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Abstract
Methods and apparatus for implementing charge skimming and variable integration time in focal plane arrays formed in a silicon substrate. The present invention provides for pulsing a field plate that lies over a diode disposed in the substrate in order to provide for charge skimming and variable integration time. The field plate is normally dc biased to suppress diode edge leakage. No additional structure is needed in the silicon substrate, and basic readout clocking is unaffected. Any interline transfer focal plane array can benefit from using the principles of the present invention.
Claims11
A focal plane array comprising a plurality of pixel elements, wherein each pixel element comprises:
- a substrate;
- a doped region connected to a diode disposed in the substrate;
- a cathode plate formed on the surface of the substrate, and wherein the substrate, doped region, and cathode plate form the diode;
- an insulating layer disposed over the cathode plate, the doped region, and the substrate;
- a field plate disposed above the cathode plate and separated therefrom by the insulating layer;
- a transfer gate disposed above the substrate that is laterally separated from the cathode plate, the doped region, and the field plate, and that is separated therefrom by the insulating layer;
- a readout gate disposed above the substrate that is laterally separated from the transfer gate and that is separated from the substrate by the insulating layer, and wherein a portion of the transfer gate overlaps the readout gate:
- and
- a controller coupled to the field plate and the transfer gate that is adapted to pulse the transfer gate to a predetermined potential relative to potentials of the field plate and substrate to transfer charge to the readout circuit and produce a predetermined amount of charge skimming in the focal plane array, and pulse the field plate with a predetermined voltage to forward bias the diode and dump charge to the substrate, reset its potential, and suppress charge integration therein, and wherein the controller is adapted to produce a field plate pulse whose relative location within a frame time determines the starting time for charge integration, wherein the size of the field plate pulse relative to the potentials of the transfer gate and the substrate determines the amount of charge that is dumped.
A method for use with a focal plane array comprising a substrate, a plurality of diodes each having a field plate disposed thereover and a transfer gate disposed adjacent thereto, and a readout circuit coupled to each diode, said method comprising the steps of:
- pulsing the transfer gate to a predetermined potential relative to potentials of the field plate and substrate to transfer charge to the readout circuit and produce a predetermined amount of charge skimming in the focal plane array, and pulsing the field plate above each of the plurality of diodes with a predetermined voltage at a predetermined time during a frame period to provide a starting time for charge integration and at a predetermined voltage level relative to the potentials of the transfer gate and substrate to forward bias the diode associated therewith and dump charge to the substrate, reset its potential, and suppress charge integration therein.
A method for use with a Schottky-barrier focal plane array comprising a substrate, a Schottky-barrier diode having a field plate disposed thereover and a transfer gate disposed adjacent thereto, and a readout circuit coupled to the Schottky-barrier diode, said method comprising the steps of:
- pulsing the transfer gate to a predetermined potential relative to potentials of the field plate and substrate to transfer charge to the readout circuit and produce a predetermined amount of charge skimming in the focal plane array, and pulsing the field plate with a predetermined voltage at a predetermined time during a frame period and at a predetermined voltage level relative to potentials of the transfer gate and the substrate to forward bias the diode to dump charge to the substrate, reset its potential, and suppress charge integration therein, and wherein the location of the field plate pulse within a frame period determines the start of charge integration, and wherein the size of the field plate pulse relative to the potentials of the transfer gate and the substrate determines the amount of charge that is dumped.
Dependencies are inferred from the claim text.