Wafer testing process of a semiconductor device comprising a redundancy circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsHong-bae Moon, Bon-youl Ku, Gi-seung Song, Tae-wook Seo
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Abstract
A wafer testing process of a semiconductor device provided with a redundancy circuit. The process comprises a step of removing a passivation film above a pad and link portion, pre-laser testing, laser-repairing, and final quality marking using an off-line inking method. Therefore, fabrication-test processes are simplified to one step by adopting the off-line inking method, thereby achieving productivity improvement, quality enhancement, and reduction of throughput time.
Claims9
A testing process for a wafer containing a plurality of semiconductor chips, each chip having first and second passivation layers, redundancy circuits with program elements and pads for electrical connection thereto, comprising the steps of:
- (a) selectively removing a first passivation layer portion disposed over said pads of each said semiconductor chip to obtain a plurality of exposed pads and selectively removing a second passivation layer portion disposed over said program elements of each said semiconductor chip;
- (b) electrically testing every chip on said wafer through said exposed pads to identify defective chips on said wafer, including identification of defective but repairable chips and defective and unrepairable chips;
- (c) repairing said repairable chips by cutting said program elements on said repairable chips with a laser beam to obtain repaired chips;
- (d) testing a sample of said repairable chips after said laser repairing step to determine a representative goodness ratio of successfully repaired repairable chips versus unsuccessfully repaired repairable chips;
- (e) quality testing all of said repairable chips, identified in step (b) and which underwent laser repair in step (c), to determine which of said repairable chips were successfully repaired and which of said repairable chips were unsuccessfully repaired, if said goodness ratio is less than a threshold value, said step of quality testing all of said repairable chips being omitted if said goodness ratio is greater than or equal to said threshold value;
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- (f) quality marking each said defective unrepairable chip and each of said unsuccessfully repaired repairable chips as determined by said quality testing step.
A wafer testing process comprising the steps of:
- (a) forming a first protective film over a semiconductor wafer having a plurality of semiconductor chips formed thereon, each said chip having at least one pad for electrical connection and at least one program element;
- (b) forming a second protective film on said first protective film, said second protective film being a final protective film for said semiconductor wafer;
- (c) removing a portion of said first and second protective films by a single photolithography step to expose said at least one pad and said at least one program element on each said chip on said wafer;
- (d) electrically testing every chip on said wafer through said exposed pads to obtain repairing information, including identification of defective but repairable chips and defective and unrepairable chips;
- (e) repairing said defective but repairable chips on said wafer according to the repairing information obtained in step (d) by cutting said program elements with a laser beam;
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- (f) quality marking defective chips on said wafer according to the repairing information obtained in step (d).
Dependencies are inferred from the claim text.