Variable rate digital filter

A digital filter apparatus having a bandwidth 1/4 of the input sample rate comprising:

• first all-pass filtering means characterized by a first coefficient having a value 18/128 coupled to receive input samples for producing a first output, said first all-pass filtering means comprising:
• a first shift register and a second shift register coupled to receive in parallel the input samples as input data, and
• a first summer which is coupled to receive first shifted data from said first shift register and to receive second shifted data from said second shift register to produce first summed data, said first shift register shifting its input data by six bits right to effect division by 64 at its output as the first shifted data, and said second shift register shifting its input data by three bits right to effect division by 8 at its output as the second shifted data such that the first summed data of said first summer is a product of 18/128 and its input samples;
• second all-pass filtering means characterized by a second coefficient having a value 75/128 coupled to receive input samples to produce a second output, said second all-pass filtering means comprising:
• a third shift register and a fourth shift register coupled to receive in parallel its input samples as its input data,
• a second summer which is coupled to receive third shifted data from said third shift register and fourth shifted data from said fourth shift register to produce second summed data,
• a fifth shift register, and
• a third summer which is coupled to receive the second summed data from said second summer and fifth shifted data from said fifth shift register,
• said third shift register shifting its input data by one bit right to effect division by 2 at its output as the third shifted data, and said second shift register shifting its input data by three bits right to effect division by 8 at its output as the fourth shifted data such that the second summed data is a product 5/8 and the input samples,
• said fifth shift register shifting its input data by four bits right such that the third summed data is a product of 75/128 and the input samples;
• means for delaying said second output of said second all-pass filtering means by one delay unit;
• and
• means for adding said first output with the output of said delaying means to produce a filter output.

A digital filter apparatus having a bandwidth 1/4 of the input sample rate comprising:

• first all-pass filtering means characterized by a first coefficient having a value 18/128 coupled to receive input samples for producing a first output, said first all-pass filtering means comprising:
• a first shift register and a second shift register coupled to receive in parallel the input samples as input data, and
• a first summer which is coupled to receive first shifted data from said first shift register and to receive second shifted data from said second shift register to produce first summed data, said first shift register shifting its input data by six bits right to effect division by 64 at its output as the first shifted data, and said second shift register shifting its input data by three bits right to effect division by 8 at its output as the second shifted data such that the first summed data of said first summer is a product of 18/128 and its input samples;
• second all-pass filtering means characterized by a second coefficient having a value 75/128 coupled to receive input samples to produce a second output, said second all-pass filtering means comprising:
• a third shift register and a fourth shift register coupled to receive in parallel its input samples as its input data,
• a second summer which is coupled to receive third shifted data from said third shift register and fourth shifted data from said fourth shift register to produce second summed data,
• a fifth shift register, and
• a third summer which is coupled to receive the second summed data from said second summer and fifth shifted data rom said fifth shift register,
• said third shift register shifting its input data by one bit right to effect division by 2 at its output as the third shifted data, and said second shift register shifting its input data by three bits right to effect division by 8 at its output as the fourth shifted data such that the second summed data is a product of 5/8 and the input samples,
• said fifth shift register shifting its input data by four bits right such that the third summed data is a product of 75/128 and the input samples;
• means for delaying said second output of said second all-pass filtering means by one delay unit;
• and
• means for adding the first output of said first all-pass filtering means with the second output of said second all-pass filtering means to produce a filter output.

A method for filtering an input signal, said method comprising:

• analog filtering said input signal to produce an analog band-limited signal having a cutoff frequency;
• sampling said analog band-limited signal only at a first sampling rate, said first sampling rate being variable relative to the cutoff frequency of said analog filtering, said sampling means being coupled to said filtering means to produce a digital sampled signal at said first sampling rate;
• accepting said digital sampled signal at said first sampling rate;
• and
• digitally filtering said digital sampled signal to produce a filtered output signal at a second sampling rate, wherein the ratio of said first sampling rate to said second sampling rate is variable.