US 5,324,966 AGranted

MOS-controlled thyristor

AssigneesToyo Denki Seizo Kabushiki Kaisha, Takashige Tamamushi

InventorsKimihiro Muraoka, Takashige Tamamushi

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Abstract

The present invention has for its object to provide a planar MOS-controlled thyristor of improved main thyristor turn-ON characteristics and a vertical MOS-controlled thyristor of improved main thyristor turn-ON characteristics and increased integration density. In the planar MOS-controlled thyristor a p-channel MOSFET for turning OFF the main thyristor and an n-channel MOSFET for turning it ON are provided in an integrated form and a channel is provided between the cathode region and a high resistance layer. The current in the channel can be controlled by the base or gate potential through utilization of the J-FET or static induction effect. In the vertical MOS-controlled thyristor a vertical p-channel MOSFET for turning OFF the main thyristor and a vertical n-channel MOSFET for turning it ON are provided in an integrated form and a base layer or channel is provided between the cathode region and a high resistivity layer. The current in the base or channel can be controlled by the base or gate potential through utilization of the base resistance effect, J-FET effect, or static induction effect.

Claims2

Dependent claims

A planar MOS-controlled thyristor which has an anode region and a cathode region provided in first and second main surfaces of a semiconductor substrate, respectively, and a gate region, a p-channel MOSFET and an n-channel MOSFET formed adjacent said cathode region in the vicinity of said first main surface of said semiconductor substrate, characterized in:

that a layer of the same conductivity type as that of said cathode region is interposed between said gate region and a region formed in contact with said cathode region and opposite in conductivity type thereto, said opposite conductivity type region and said gate region serving as main electrodes of said p-channel MOSFET which uses said same conductivity type layer as its channel;
that said n-channel MOSFET is formed between said same conductivity type layer and a high resistivity layer, said n-channel MOSFET using said same conductivity type layer and said high resistivity layer as its main electrodes and said gate region as its channel;
that a channel region is formed perpendicularly to said substrate surfaces between said cathode region and said high resistivity layer to control the flow of electrons which are injected from said cathode region;
that said channel region is surrounded and essentially depleted by said gate region, the potential in said channel region varying with the potential of said gate region by a static induction effect;
and
that said p-channel MOSFET and said n-channel MOSFET have a common gate electrode formed over said first main surface of said substrate with an insulating layer interposed therebetween, said common gate electrode extending from a position just above a little inside of said opposite conductivity type region to a position above the marginal edge of said high resistivity layer, crossing over said same conductivity type layer and said gate region, and that a cathode electrode is formed shorting said cathode region and said opposite conductivity type region.

3 more elements

A vertical MOS-controlled thyristor which has a cathode region and an anode region formed in first and second main surfaces of a semiconductor substrate, respectively, and a gate region, a substantially vertical p-channel MOSFET and a substantially vertical n-channel MOSFET formed adjacent said cathode region in the vicinity of said first main surface of said semiconductor substrate, characterized in:

that a layer of the same conductivity type as that of said cathode region is formed between said gate region and a region formed in contact with said cathode region and opposite in conductivity type thereto, said opposite conductivity type region and said gate region serving as main electrodes of said p-channel MOSFET which uses said same conductivity layer as its channel;
that said n-channel MOSFET is formed between said same conductivity type layer and a high resistivity layer, said n-channel MOSFET using said same conductivity type layer and said high resistivity layer as its main electrodes and said gate region as its channel;
that a channel region is formed perpendicularly to said substrate surfaces between said cathode region and said high resistivity layer to control the flow of electrons which are injected from said cathode region;
that said channel region is surrounded and essentially depleted by said gate region, the potential in said channel region varying with the potential of said gate region by a J-FET or static induction effect;
and
that said p-channel MOSFET and said n-channel MOSFET have a common gate electrode formed in a trench cut in said first main surface of said semiconductor substrate substantially perpendicularly thereto and extending down past said opposite conductivity type region, said same conductivity type layer and said gate region and into said high resistivity layer, and insulating layer being interposed between said common gate electrode and the side wall of said trench, and that a cathode electrode is formed shorting said cathode region and said opposite conductivity type region.

3 more elements

Dependencies are inferred from the claim text.