US 5,323,158 AGranted

Switched capacitor one-bit digital-to-analog converter

AssigneeAnalog Devices, Inc.

InventorPaul F. Ferguson, Jr.

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Abstract

A switched capacitor one-bit digital-to-analog converter is preferably utilized in the feedback path of a sigma delta modulator. The one-bit digital-to-analog converter includes first and second capacitors, a first switching circuit for coupling charge from a reference source to the capacitors, and a second switching circuit for coupling charge from the capacitors to positive and negative outputs, such as the summing junction of an operational amplifier. The switches in the second switching circuit have a cross-coupled configuration and are controlled by data dependent control signals. The data dependent control signals are structured such that charge is coupled from the capacitors to the summing junction on both clock phases, regardless of the state of the data. As a result, the sizes of the capacitors can be reduced by a factor of two for the same charge transfer.

Claims10

Dependent claims

A switched capacitor one-bit digital-to-analog converter comprising:

first and second capacitors, each having a first lead and a second lead;
first switching means connected to the first leads of said capacitors for coupling charge from a reference source to said capacitors;
second switching means connected to the second leads of said capacitors for coupling charge from said capacitors to a positive output and a negative output, comprising a first switch connected between said first capacitor and said positive output, a second switch connected between said second capacitor and said negative output, a third switch connected between said first capacitor and said negative output, and a fourth switch connected between said second capacitor and said positive output;
means for applying a first control signal to said first and second switches, said first control signal comprising .PHI..sub.2 .cndot.X+.PHI..sub.1 .cndot.XI, where .PHI..sub.1 and .PHI..sub.2 represent clock phase 1 and clock phase 2, respectively, X and XI represent input data and inverted input data, respectively, ".cndot." represents a logical AND operation, and "+" represents a logical OR operation;
and
means for applying a second control signal to said third and fourth switches, said second control signal comprising .PHI..sub.1 .cndot.X+.PHI..sub.2 .cndot.XI.

3 more elements

A sigma delta modulator comprising:

an integrator having a summing junction and providing an integrator output signal;
a comparator responsive to said integrator output signal for providing a comparator output signal having a first state when said integrator output signal is greater than a reference level and a second state when said integrator output signal is less than the reference level;
a switched capacitor one-bit digital-to-analog converter responsive to said comparator output signal for providing an error signal to said summing junction, said one-bit digital-to-analog converter comprising,
first and second capacitors, each having a first lead and a second lead;
first switching means connected to the first leads of said capacitors for coupling charge from a reference source to said capacitors;
second switching means connected to the second leads of said capacitors for coupling charge from said capacitors to a positive output and a negative output, comprising a first switch connected between said first capacitor and said positive output, a second switch connected between said second capacitor and said negative output, a third switch connected between said first capacitor and said negative output, and a fourth switch connected between said second capacitor and said positive output;
means for applying a first control signal to said first and second switches, said first control signal comprising .PHI..sub.2 .cndot.X+.PHI..sub.1 .cndot.XI, where .PHI..sub.1 and .PHI..sub.2 represent clock phase 1 and clock phase 2, respectively, X and XI represent input data and inverted input data, respectively, ".cndot." represents a logical AND operation, and "+" represents a logical OR operation;
and
means for applying a second control signal to said third and fourth switches, said second control signal comprising .PHI..sub.1 .cndot.X+.PHI..sub.2 .cndot.XI;
and
a switched capacitor input circuit for coupling an input signal to said summing junction.

8 more elements

Dependencies are inferred from the claim text.