US 5,323,157 AGranted

Sigma-delta digital-to-analog converter with reduced noise

AssigneeMotorola, Inc.

InventorsRobert C. Ledzius, James S. Irwin

Life of this patent

Estimating the term…

Loading patent…

Abstract

A sigma-delta digital-to-analog converter (DAC) (40) receives oversampled input data representative of an analog signal. The data may be optionally interpolated to a higher rate in a interpolator (41). A noise-shaping sigma-delta modulator (42) is connected to the output of the interpolator (41). The output of the modulator (42) is provided to a finite impulse response (FIR) filter (43). The FIR filter (43) has a frequency response characteristic which reduces the shaped noise and aliased components. This noise has a tendency to intermodulate back into the DAC's passband. The FIR filter (43) uses a series of flip-flops (81, 82, 83) functioning as delay elements with well-controlled timing edges. The outputs of the flip-flops (81, 82, 83) control current sources (91, 92, 93) weighted according to corresponding filter coefficients. The outputs of the current sources (91, 92, 93) are then summed in a summing device such as an amplifier (101).

Claims10

Dependent claims

A sigma-delta digital-to-analog converter with reduced noise comprising:

a sigma-delta modulator having n input for sequentially receiving first digital data words, a clock input terminal for receiving a modulator clock signal, and an output terminal for providing a modulator output signal having a value in a passband of the digital-to-analog-converter corresponding to said first digital data words;
and
a finite impulse response (FIR) filter having an input coupled to said output terminal of said sigma-delta modulator, and an output for providing an analog signal;
said FIR filter shaping said second analog signal according to a predetermined transfer function, thereby decreasing intermodulated noise in said passband of the sigma-delta digital-to-analog converter, wherein said FIR filter comprises:
a plurality of delay elements ordered from a first delay element to a last delay element, said first delay element having an input for receiving said modulator output signal, each delay element besides said first delay element having an input coupled to an output of a preceding delay element, each delay element delaying an input thereof by one period of said modulator clock to provide a delayed signal at an output thereof;
a plurality of amplifier means corresponding to each of said plurality of delay elements, each amplifier means having an input coupled to an output of a corresponding one of said plurality of delay elements, and an output, said plurality of delay elements having gains to implement said predetermined transfer function, wherein each of said amplifier means comprises a controlled current source;
and
a summing device having inputs coupled to each of said output terminals of said plurality of delay elements, and an output terminal for providing said analog signal.

5 more elements

A sigma-delta digital-to-analog converter with reduced noise comprising:

a sufficiently-resolved sigma-delta modulator having an input for receiving first digital data words, a clock input terminal for receiving a modulator clock signal, and an output terminal for providing an output having a plurality of bits including first and second bits;
said first output bit corresponding to a most-significant bit of said output;
said second bit corresponding to a tap bit which is not said most significant or a second most-significant bit of said output;
a first finite impulse response (FIR) filter having an input for receiving said first output bit, and an output for providing a first analog output signal;
a second FIR filter having an input for receiving said second output bit, and an output for providing a second analog signal;
means for weighting an output of said second FIR filter according to a relative significance of said second output bit compared to said first output bit;
and
summing means coupled to said first and second FIR filters, for summing said first and second analog output signals to provide a third analog output signal which is an output sigma of the sigma-delta digital-to-analog converter;
said first and second FIR filters filtering said first and second bits, respectively, according to predetermined transfer functions, thereby decreasing a potential for intermodulated noise in said passband of the sigma-delta digital-to-analog converter.

6 more elements

Dependencies are inferred from the claim text.