Method for error correction of software errors in a communication system

A communication system, having;

• a switching network for through-connection of calls, connector modules connected to the switching network and having first processors and first local memory systems allocated respectively to the first processors,
• a multiprocessor system for central system control and having a central system bus connected to second processors having second local memory systems allocated respectively to the second processors, and connected to a memory system shared by all second processors of the multiprocessor system,
• a signaling channel connector module for the control of a central signaling channel and having third processors and third local memory systems allocated respectively to the third processors, said signaling channel connector module connected to the switching network,
• further connector modules for connecting the multiprocessor system to external input/output devices and having fourth processors and fourth local memory systems allocated respectively to the fourth processors,
• each of the further connector modules connected to the central system bus in the multiprocessor system, and
• patch procedures for correcting software errors of procedures/data residing in the communication system,
• comprising:
• a patch command having a plurality of sub-components and a plurality of destination addresses input by at least one input/output device;
• a means for branching to patch processes residing in respective memory systems of the connector modules, the signaling channel connector module and the further connector modules, and of the multiprocessor system after evaluation of the destination addresses, and, for use after evaluation of the sub-components,
• means for editing information data corresponding to code modifications in conformity with the multiprocessor system, the means for editing information occurring in a first step as an integral component part of the patch command, and
• means for exclusively reserving by further patch processes at least one of the first processors of the connector modules, the signaling channel connector module and the further connector modules and of the multiprocessor system in a second step, said further patch processes including a first patch process having a lower priority level than regular processes allocated to normal operation of the communication system accesses at least one of the first processors of the connector modules, the signaling channel connector module and the further connector modules only when all regular processes of a high priority level sequencing on the respective processor have terminated and said further patch processes including, following immediately the first patch process, a second patch process having a priority level exceeding the priority levels of the regular processes allocated to the normal operation of the communication system installs edited code modifications and, has another priority level, such that the second patch process can not be interrupted by regular processes having the lower priority levels, and
• means for returning exclusively reserved processors to the regular processes of the communication system in a third step after a conclusion of the patch processes.