US 5,317,753 AGranted

Coordinate rotation digital computer processor (cordic processor) for vector rotations in carry-save architecture

AssigneeSiemens Aktiengesellschaft

InventorsRonald Kuenemund, Tobias Noll

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Abstract

A CORDIC processor is provided in carry-save architecture in connection with intense pipelining for vector rotations, particularly given problems in real-time processing. The processor comprises a plurality of vector iteration stages and a plurality of angle iteration stages that are partially redundantly present in order to guarantee a convergency of the CORDIC algorithm despite an ambiguity region in the sign detection of carry-save numbers and in order to simplify other circuit components, for example a multiplier. As a result of the carry-save architecture, only incomplete addition/subtraction operations are executed in the iteration stages, and intermediate results in the form of carry and save words are fed through the CORDIC processor on separate line paths until they are added in an adder at the processor output to form the final result vector. The invention is advantageous in the low chip surface requirement that results from a high regularity of the overall structure and from simply-constructed base cells of the vector and angle iteration stages and in the extremely-high processing speed that results from the combination of intense pipelining and the carry-save architecture.

Claims8

Dependent claims

A coordinate rotation digital computer processor for vector rotations, particularly for solving real-time processing of a vector of the vector components X.sub.0, Y.sub.0, by an angle Z.sub.0, where X.sub.0, Y.sub.0 and Z.sub.0 are each digital words having a plurality of data bits, said data bits having particular significances relative to one another, said processor comprising:

a vector path comprising a plurality of series-connected clocked vector iteration stages, a first of said vector iteration stages including vector inputs for exclusively receiving the vector components X.sub.0, Y.sub.0 ;
an angle path including a plurality of series-connected clocked angle iteration stages, a first of said angle iteration stages including angle inputs for exclusively receiving the data bits describing the angle Z.sub.0 ;
a plurality of transmission gates between said vector iteration stages;
a plurality of registers between said angle iteration stages;
each of said vector iteration stages and said angle iteration stages comprising addition/subtraction circuits for providing, during a clock interval, only incomplete addition/subtraction operations with only intermediate results at the end of a clock interval in the form of a carry word of carry bits and a separate sum word of sum bits for further processing;
said plurality of vector iteration stages and said plurality of angle iteration stages each further comprising shift means for shifting the carry and sum bits;
said plurality of angle iteration stages further comprising sign detectors using the carry and sum bits to detect the sign of the respective intermediate results;
said plurality of series-connected vector iteration stages comprising a last stage of the series including inputs for the respective carry and sum words XC.sub.n, YC.sub.n, XS.sub.n, YS.sub.n ;
a multiplier including respective inputs and outputs, said inputs connected to said outputs of said last stage of said plurality of series-connected vector iteration stages for multiplying the output carry and sum words of the respective vector components XC.sub.n, XS.sub.n, YC.sub.n, YS.sub.n by a predetermined correction factor K;
and
added means connected to said outputs of said multiplier for adding the carry and sum words output therefrom to form components of a result vector X.sub.N, Y.sub.N.

8 more elements

a vector path comprising a plurality of series-connected clocked vector iteration stages, a first of said vector iteration stages including vector inputs for receiving the vector components X.sub.0, Y.sub.0 ;
an angle path including a plurality of series-connected clocked angle iteration stages, a first of said angle iteration stages including angle inputs for receiving the data bits describing the angle Z.sub.0 ;
a plurality of transmission gates between said vector iteration stages;
a plurality of registers between said angle iteration stages;
each of said vector iteration stages and said angle iteration stages comprising addition/subtraction circuits for providing, during a clock interval, only incomplete addition/subtraction operations with intermediate results at the end of a clock interval in the form of a carry word of carry bits and a sum word of sum bits for further processing;
said plurality of vector iteration stages and said plurality of angle iteration stages each further comprising shift means for shifting the carry and sum bits;
said plurality of angle iteration stages further comprising sign detectors using the carry and sum bits to detect the sign of the respective intermediate results;
said plurality of series-connected vector iteration stages comprising a last stage of the series including inputs for the respective carry and sum words XC.sub.n, YC.sub.n, XS.sub.n, YS.sub.n ;
a multiplier including inputs and outputs, said inputs connected to said outputs of said last stage of said plurality of series-connected vector iteration stages for multiplying the output carry and sum words of the respective vector components XC.sub.n, XS.sub.n, YC.sub.n, YS.sub.n by a predetermined correction factor K;
adder means connected to said outputs of said multiplier for adding the carry and sum words output therefrom to form components of a result vector X.sub.N, Y.sub.N wherein each of said vector base cells comprises:
first and second multiplexers each including inputs and outputs;
first, second, third and fourth full adders each including inputs and outputs;
said transmission gates between said vector iteration stages including ten clocked transmission gates each including an input and an output;
an input line for a sum bit of a first vector component X connected to a first of said inputs of said first full adder;
an input line for a sum bit of a second vector component Y connected to a first input of said second full adder;
an input line for a carry bit of the first vector component X is connected to a first input of said third full adder via a first of said clocked transmission gates clocked by a first clock signal;
an input line for a carry bit of the second vector component Y is connected to a first input of said fourth adder via a fourth of said clocked transmission gates clocked by the first clock signal;
an input line for an i-times more-significant carry bit of the second vector component Y is connected to a first of said inputs of said first multiplexer and via said first multiplexer and a first output thereof to a second input of said first full adder;
an input line for an i-times more-significant sum bit of the second vector component Y is connected to a second input of said first multiplexer via said first multiplexer and a second output thereof to a third input of said first full adder;
an input line for the i-times more-significant carry bit of the first vector component X is connected to a first input of said second multiplexer and via said second multiplexer and a first output thereof to a second input of said second full adder;
an input line for the i-times more-significant sum bit of the first vector component X is connected to a second input of said second multiplexer and via said second multiplexer and a second input thereof to a third input of said second full adder;
said multiplexers connected to receive the sign bits from respective corresponding immediately-preceding angle path iteration stages and operable in response thereto to invert or non-invert carry and sum bits applied thereto depending on the sign signal;
said outputs of said full adders being a sum output and a carry output;
said output of said first full adder connected to said second input of said third full adder via a second of said clocked transmission gates;
said sum output of said second full adder connected to a second input of said fourth full adder via a fifth of said clocked transmission gates, said second and fifth transmission gates clocked by the first clock signal;
an output line for a first-stage carry bit of the first vector component X is connected via a third of said transmission gates as a carry output of said first full adder;
an output line for a first-stage carry bit of the second vector component Y is connected via a sixth of said transmission gates as a carry output of said second full adder, said second and sixth transmission gates clocked by the first clock signal;
an input line for a first-stage carry bit of the first vector component X from the next less-significant vector base cell is connected to a third output of said first full adder;
an input line for a first-stage carry bit of the second vector component Y of the next less-significant vector base cell is connected to a third input of said fourth full adder;
an input line for a second-stage carry bit of the first vector component X and the second vector component Y are looped through the vector base cell from a next less-significant vector base cell to provide outputs for an immediately-following vector iteration stage vector base cell;
said sum output of said third full adder is connected via a seventh of said clocked transmission gates as a cell output line for a sum bit of the first vector component X of an immediately-following vector iteration stage;
said output of said fourth full adder is connected via a ninth of said clock transmission gates as a cell output line for a sum bit of the second vector component Y of the immediately-following vector iteration stage, said seventh and ninth transmission gates being clocked by the second clock signal;
said carry output of said third full adder is connected via an eighth of said clocked transmission gates to provide a carry output line for a second-stage carry bit of the first vector component X;
and
said carry output of said fourth full adder is connected via a tenth of said clocked transmission gates to provide a carry output line for a second-stage carry bit of the second vector component Y, said eighth and tenth transmission gates being clocked by the second clock signal.

32 more elements

a vector path comprising a plurality of series-connected clocked vector iteration stages, a first of said vector iteration stages including vector inputs for receiving the vector components X.sub.0, Y.sub.0 ;
an angle path including a plurality of series-connected clocked angle iteration stages, a first of said angle iteration stages including angle inputs for receiving the data bits describing the angle Z.sub.0 ;
a plurality of transmission gates between said vector iteration stages;
a plurality of registers between said angle iteration stages;
each of said vector iteration stages and said angle iteration stages comprising addition/subtraction circuits for providing, during a clock interval, only incomplete addition/subtraction operations with intermediate results at the end of a clock interval in the form of a carry word of carry bits and a sum word of sum bits for further processing;
said plurality of vector iteration stages and said plurality of angle iteration stages each further comprising shift means for shifting the carry and sum bits;
said plurality of angle iteration stages further comprising sign detectors using the carry and sum bits to detect the sign of the respective intermediate results;
said plurality of series-connected vector iteration stages comprising a last stage of the series including inputs for the respective carry and sum words XC.sub.n, YC.sub.n, XS.sub.n, YS.sub.n ;
a multiplier including inputs and outputs, said inputs connected to said outputs of said last stage of said plurality of series-connected vector iteration stages for multiplying the output carry and sum words of the respective vector components XC.sub.n, XS.sub.n, YC.sub.n, YS.sub.n by a predetermined correction factor K;
adder means connected to said outputs of said multiplier for adding the carry and sum words output therefrom to form components of a result vector X.sub.N, Y.sub.N wherein at least one vector iteration stage and at least one angle iteration stage are redundantly provided in order to provide, given a required accuracy of a final result vector, greater ambiguity regions in sign detection in the individual angle iteration stages and in order to simultaneously enable an identical correction factor K for all combinations of processor input signals and further wherein a given accuracy and the number of redundantly-provided vector and angle iteration stages is such that four most significant carry and sum bits of a respective immediately-preceding angle iteration stage are required for sign detection wherein each of said sign detectors comprises an optimized sign detector for all of said angle iteration stages which form a sign output signal of that sign detector from the four most-significant carry and sum bits of the respect immediately-preceding angle iteration stage and of a non-inverted sign output signal of the respective immediately-preceding angle iteration stage and, comprising:
an EQUIVALENCE gate including first and second inputs and an output, said second input connected to receive a sign output signal from an immediately-preceding angle iteration stage;
a first EXCLUSIVE-OR gate including a first input connected to said output of said EQUIVALENCE gate, a second input, and an output having the sign output signal of said sign detector;
a second EXCLUSIVE-OR gate including first and second inputs for respectively receiving the most-significant carry and sum bits, and an output connected to said first input of said EQUIVALENCE gate;
a NOR gate and a first NAND gate each including a first input connected to receive the second most-significant carry bit, a second input for receiving the second most-significant sign bit, and an output;
a second NAND gate including a first input connected to said output of said first NAND gate, a second input, and an output;
a first OR-NAND gate including a first input connected to said output of said NOR gate, a second input connected in common with said second input of said second NAND gate, and a third input connected to said output of said second NAND gate, and an output connected to said second input of said first EXCLUSIVE-OR gate;
a third NAND gate including first and second inputs respectively connected to receive the third most-significant carry and sum bits, and an output;
a second OR-NAND gate including a first input and a second input for respectively receiving the third most-significant carry and sum bits, a third input connected to said output of said third NAND gate, and an output;
a third OR-NAND gate including a first input connected to said output of said second OR-NAND gate, a second input connected with said third input of said second OR-NAND gate to said output of said third NAND gate, a third input, and an output connected to said second inputs of said first OR-NAND gate and said second NAND gate;
and
a fourth NAND gate including an output connected to said third input of said third OR-NAND gate, and first and second inputs respectively connected to receive the fourth most-significant carry and sum bits.

18 more elements

Dependencies are inferred from the claim text.