Minimal interrupt latency scheme using multiple program counters
AssigneeZilog, Inc.
InventorStephen H. Chan
Life of this patent
Estimating the term…
Abstract
A method and apparatus for using multiple program counters to reduce the latency time of a computer in response to an interrupt or subroutine call using a memory with multiple memory locations for storing the multiple program counters and control means in order to choose which one of the memory locations is used as a current program counter. Additionally, the use of a memory location to store the starting address of the interrupt subroutine is also disclosed.
Claims14
A program counter apparatus for reducing the latency time of a computer in response to an interrupt, said apparatus comprising:
- a memory having memory locations, wherein a general program counter value is located at one of said memory locations and alternate program counter values are located at a number of other of said memory locations;
- and
- control means connected to said memory for controlling which one of said memory locations contains the current program counter value.
A method for reducing the latency time of a computer in response to interrupts from interrupt devices, said computer including a memory with a plurality of memory locations, said method comprising the steps of:
- (a) establishing a general program counter value located at a first of said memory locations in said memory, establishing alternate program counter values associated with the interrupt devices, said alternate program counter values located at other memory locations in said memory and setting the location of the current program counter value as the first memory location containing the general program counter value;
- (b) prioritizing the interrupts received from the interrupt devices to choose one of the interrupt devices to be serviced by executing its associated subroutine;
- (c) a switching the location of the current program counter value from the first memory location containing the general program counter value to another memory location containing the alternate program counter value associated with the chosen interrupt device;
- (d) thereafter, executing the interrupt subroutine associated with the chosen interrupt device;
- and
- (e) subsequently, switching the location of the current program counter value back from the another memory location containing the alternate program counter value associated with the chosen interrupt device to the first memory location containing the general program counter.
A program counter apparatus for reducing the latency time of a computer in response to a subroutine call, said apparatus comprising:
- a memory having memory locations, wherein a general program counter value is located at one of said memory locations and alternate program counter values are located at a number of other of said memory locations;
- and
- control means connected to said memory for controlling which one of said memory locations contains the current program counter value.
Dependencies are inferred from the claim text.