Method of synchronizing parallel processors employing channels and compiling method minimizing cross-processor data dependencies

In a multiprocessor having first and second parallel processors for performing sequential operations specified in respective first and second instruction streams having cross-stream data dependencies, a register channel accessible by said processors characterized by a synchronization bit indicating whether said register channel has been written to, and a memory accessible to said processors not having a synchronization bit, the method of passing plural cross-stream dependent data between said processors in a synchronizing fashion comprising:

• first writing, by said first processor to said memory, first cross-stream dependent data available to said first processor;
• second writing, by said first processor to said register channel, not earlier than said first writing, second cross-stream dependent data available to said first processor;
• waiting, if necessary, by said second processor until said synchronization bit indicates that said second writing has occurred;
• first reading, by said second processor, the second cross-stream dependent data from said register channel;
• and
• second reading, by said second processor, not earlier than said first reading of the first cross-stream dependent data from said memory.

In a multiprocessor having first, second and third parallel processors for performing sequential operations specified in respective first, second and third instruction streams having cross-stream data dependencies, first and second register channels accessible by said processors each characterized by a synchronization bit indicating whether said register channel has been written to, and a memory accessible to said processors not having a synchronization bit, the method of passing plural cross-stream dependent data between said processors in synchronizing fashion comprising:

• first writing, by said first processor to said memory, first cross-stream dependent data available to said first processor;
• second writing by said first processor to said first register channel, not earlier than said first writing, second cross-stream dependent data available to said first processor;
• first waiting, if necessary, by said second processor until said synchronization bit of said first register channel indicates that said second writing has occurred;
• first reading by said second processor of the second cross-stream dependent data from said first register channel;
• third writing, by said second processor to said second register channel, not earlier than said second reading, third cross-stream dependent data available to said second processor;
• second waiting, if necessary, by said third processor until said synchronization bit of said second register channel indicates that said third writing has occurred;
• second reading, by said third processor, the third cross-stream dependent data from said second register channel;
• and
• third reading by said third processor, not earlier than said second reading, the first cross-stream dependent data from said memory.

In a multiprocessor having a plurality of parallel processors for performing sequential operations specified respectively in a plurality of instruction streams having cross-stream data dependencies, a plurality of register channels accessible by said processors for synchronizing data passing between said processors, and a memory accessible to said processors for non-synchronizing data passing between said processors, the method for passing plural cross-stream dependent data between processors in a synchronized fashion comprising:

• first writing, by one of said processors to said memory means, first cross-stream dependent data available to said first processor;
• last reading said first cross-stream dependent data from said memory means by another of said processors;
• and
• enforcing other cross-stream data dependencies by a sequence of one or more writing-reading pairs associated respectively with one or more register channels, said sequence beginning with a second writing to a register channel, not earlier than said first writing, and ending with a next-to-last reading, from the same or different register channel not later than said last reading.