Multiple-processor computer system with asynchronous execution of identical code streams

A method of operating a computer system having multiple processors, each processor having a local memory which is not accessible by the other processors, input/output (I/O) means for providing data to and from one or more external devices, and a plurality of vote circuits coupled between the I/O means and the processors, comprising the steps of:

• a) clocking each of said processors independently of one another whereby said processors may vary in clock cycle;
• b) during said independent clocking, executing the same instruction stream in each one of the processors;
• c) in executing said instruction stream, accessing by each processor its local memory;
• d) in executing said instruction stream, presenting output data separately to an output storage buffer and from the output storage buffer to an output port of each processor, said output data being outbound processor data issued from each of said processors;
• and
• e) receiving the output data from all said ports in each of said plurality of vote circuit asynchronously to one or more of said processors and voting said output data, wherein a copy of said outbound processor data is passed through from said issuing processors to said I/O means only when said vote circuit detects identical outbound processor data from a majority of said issuing processors.

A method of operating a computer system having multiple processors and communicating data to and from one or more external devices, comprising the steps of:

• a) executing the same instruction stream in at least first and second processors, said first and second processors being clocked independently whereby execution of instructions of said instruction stream may be at different rates;
• b) during said executing, generating remote access requests in each of said first and second processors for access to said one or more external devices and temporarily storing outbound processor data from each processor in a separate storage buffer, the remote access requests being directed to separate first and second access ports corresponding to said first and second processors;
• and
• c) detecting each one of said remote access requests at said first and second access ports, waiting until a remote access request is detected at both the first and second access ports, then voting said remote access, wherein said voting is preformed asynchronously with respect to said clocking of said respective processors;
• and
• d) passing along said outbound processor data if both remote access requests are the same, and if identical outbound processor data is detected from both of said issuing processors.

A computer system for processing an instruction stream and communicating data to and from one or more external devices, comprising:

• a) first and second processors executing the same instruction stream, said first and second processors being clocked independently whereby execution of said instruction stream may be at different rates;
• b) means, including first and second storage buffers each having first and second access ports, for generating remote access requests for access to said one or more external devices in response to requests in each of said first and second processors, said storage buffers temporarily storing said remote access requests, the remote access requests being directed to said first and second access ports of each buffer;
• and
• c) first and second voter means for detecting said remote access requests at said first and second access ports of respective first and second buffers, each said voter means waiting until a remote access request is detected at both the first and second access ports before voting said remote access requests and passing along said remote access request if both are the same, wherein said voting of the remote access requests are performed asynchronously between said processors.

A multiple processor system for processing instructions and communicating with one or more external devices, comprising:

• a) multiple independent clocking means, respectively coupled to each processor, for providing independent clock signals to each processor whereby each processor may execute said instructions at a different rate;
• b) memory means for storing instructions coupled to each of said processors, the memory means storing substantially the same instruction stream for execution by each one of the processors;
• c) multiple FIFO buffer means, respectively coupled to each one of said processors for storage of output data, said output data being outbound processor data issued from each of said processors, said FIFO buffer means receiving said output data at the clock timing of the clock signals of said respective processor and outputting said data asynchronously thereto;
• d) voter means, coupled to receive data from each of said FIFO buffer means for all of said processors, for comparing output data from each of said processors, the voter means producing a voted output when all of said processors have produced the same output data from said separate FIFO buffer means;
• and
• e) input/output (I/O) means for coupling said voter means to said one or more external devices and coupled to receive said voted output, wherein said produced voted output is an identical copy of said output data stored in said FIFO buffer means, and a copy of said outbound processor data is passed through from said issuing processors to said I/O means when said voter means detects identical outbound processor data from all of said issuing processors.