Simplex sequence controller
AssigneeHelix Research & Development, Inc.
InventorStephen R. Clippard
Life of this patent
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Abstract
A simplex sequence controller for transmittal of output data is disclosed and includes a time base generator for generating a timing signal, a memory device having a plurality of addressable sequential storage locations for storing a sequence of data pattern with a plurality of output lines and a plurality of input address lines connected to the storage locations, along with an addressing apparatus connected to the memory device input address lines for directing access to predetermined storage locations at predetermined points in the data sequence, and address reset apparatus providing feedback from a first predetermined one of the output lines of the memory device to the addressing apparatus to direct access to a predetermined initial data sequence for output from the memory.
Claims15
A simplex sequence controller for transmittal of output data of user specified duration and content, comprising
- a time base generator for generating a timing signal and including means for determining the pulse duration of said output data;
- memory means having a plurality of addressable sequential storage locations for storing a sequence of data patterns within each said storage location for random access thereof, said memory means including
- a plurality of output lines connected to said storage locations, and
- a plurality of input address lines connected to said storage locations;
- addressing means connected to said memory means input address lines for directing access to predetermined memory means storage locations at predetermined points in said data sequence;
- and
- address reset means providing feedback from a first predetermined one of said output lines of said memory means to said addressing means to direct access to a predetermined initial data sequence for output from said memory means.
A simplex sequence controller for transmittal of data of user specified duration and content from a programmed memory device, comprising
- timing means providing timing interval signals for timing intervals of predetermined length,
- memory means for storing in chronological order a data sequence in the form of output data patterns, said data sequence being stored in a plurality of addressable sequential storage locations within said memory means,
- means for retrieving said data sequence from said plurality of said sequential memory locations upon receipt of a predetermined signal, and
- means for resetting said data sequence retrieving means for a subsequent data sequence retrieval operation.
Dependencies are inferred from the claim text.