Method and apparatus to disable ISA devices for EISA addresses outside the ISA range

An apparatus comprising:

• a bus which includes a first control line and a plurality of address lines;
• a second control line;
• first means for applying an address to said address lines of said bus and for applying a control signal to one of said first and second control lines;
• second means selectively operable in first and second modes, wherein in said first mode said second means effects application of signals from said second control line to said first control line, and in said second mode said second means effects application of signals from said first control line to said second control line, said second means including means responsive to said address lines and said first and second control lines for causing said second means to operate in said first mode in response to sad control signal being applied to said second control line when the address on said address lines is within a predetermined group of addresses, for causing said second means to operate in a mode other than said first mode in response to said control signal being applied to said second control line when the address on said address lines is outside said predetermined group of addresses, and for causing said second means to operate in said second mode in response to said control signal being applied to said first control line regardless of the address on said address lines;
• wherein said second means includes first and second buffers which each have a data input, a data output and a control input, said first buffer having its data input connected to said first control line and its data output connected to said second control line, and said second buffer having its data output connected to said second control line and its data output connected to said first control line, said second means applying an actuating signal to said control input of said first buffer to effect said application of said control signal from said first control line to said second control line, and said second means applying an actuating signal to said control input of said second buffer to effect said application of said control signal from said second control line to said first control line;
• wherein said second means includes first gate means having an input coupled to said first control line and having an output, second gate means having an input coupled to said second control line and having an output, address monitoring means for determining whether an address present on said address lines is within said predetermined group of addresses, first detecting means coupled to said output of said first gate means and responsive to an output signal from said first gate means for disabling said second gate means and for applying said actuating signal to said control input of said first buffer, and second detecting means coupled to said address monitoring means and said output of said second gate means for disabling said first gate means and for applying said actuating signal to said control input of said second buffer in response to an output signal from said second gate means when an address on said address lines id determined by said address monitoring means to be within said predetermined group of addresses;
• wherein said first gate means includes a first AND gate means a first input which is said data input of said first gate means, having a second input, and having an output which is said output of said first gate means;
• wherein said first detecting means includes a second AND gate having a first input which is coupled to said first control line, having a second input and having an output, includes a first OR gate having two inputs which are respectively coupled to said output of said first and second AND gates and having an output, and includes a first inverter having an input coupled to said output of said first OR gate and having an output;
• wherein said second gate means includes a third AND gate having a first input which is said data input of said second gate means, having a second input, and having an output which is said output of said second gate means;
• wherein said second detecting means includes a fourth AND gate having a first input coupled to said second control line, having a second input and having an output, includes a second OR gate having two inputs respectively coupled to said outputs of said third and fourth AND gates and having an output, and includes a second inverter having an input coupled to said output of said second OR gate and having an output;
• wherein said output of said second OR gate is coupled to said second input of said second AND gate, said output of said first inverter is coupled to said second input of said third AND gate, said output of said second OR gate is coupled to said second input of said fourth AND gate, and said output of said second inverter is coupled to said second input of said first AND gate;
• wherein said first detecting means includes further means responsive to a signal at said output of said first OR gate for applying the actuating signal to said control input of said first buffer;
• wherein said second detecting means includes further means responsive to a signal at said output of said second OR gate when said address monitoring means has determined that an address on said address lines is within said predetermined group for applying the actuating signal to said control input of said second buffer;
• wherein said bus includes an address valid line;
• wherein said address monitoring means includes a fifth AND gate having a plurality of inputs coupled to respective most significant bits of said address lines and having an output, includes a sixth AND gate having two inputs which are respectively coupled to said output of said fifth AND gate and to said address valid line and having an output, includes a third OR gate having first, second and third inputs and having an output, said second input of said third OR gate being coupled to said output of said sixth AND gate, includes a seventh AND gate having two inputs respectively coupled to said output of said fifth AND gate and said output of said third OR gate, and having an output coupled to said first input of said third OR gate, includes a fourth OR gate having first and second inputs which are respectively coupled to said first and second control lines and having an output, includes an eighth AND gate having inputs which are respectively coupled to said output of said third OR gate and said output of said fourth OR gate, includes a ninth AND gate having a first input coupled to said output of said fourth OR gate, having a second input, and having an output, includes a fifth OR gate having two inputs respectively coupled to said outputs of said eighth and ninth AND gates and having an output coupled to said second input of said ninth AND gate, includes a third inverter having an input coupled to said output of said fifth OR gate and having an output, and includes a tenth AND gate having two inputs respectively coupled to said output of said third OR gate and said output of said third inverter and having an output coupled to said third input of said third OR gate, said further means of aid second detecting means being responsive to a signal at said output of said second OR gate occurring simultaneously with a signal at an output of said fifth OR gate for applying the actuating signal to said control input of said second buffer;
• wherein said further means to said first detecting means includes an AND gate having a first input coupled to said output means of said first OR gate, a second input coupled to said first control line, and an output coupled to said control input of said first buffer;
• and wherein said further means of said second detecting means includes an eleventh AND gate having three inputs respectively coupled to said output of said second OR gate, said second control line and said output of said fifth OR gate and having an output coupled to said control input of said second buffer.