Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics

A reduced instruction set processing (RISC) system comprising:

• a set of high performance devices including a RISC processor unit coupled to a Local bus;
• a program storage unit coupled to said Local bus and to said processor unit by an instruction bus;
• a data storage unit coupled to said Local bus;
• and at least one data transfer controller (DTC) that is coupled to said Local bus and to a Remote bus, said DTC having means for performing overlapped input/output, whereby the DTC can simultaneously service a second I/O request from said processor unit before the completion of a first I/O request, completing both I/O requests without interruption, said Remote bus being coupled to a second set of devices have a comparatively lower performance level than said first set of devices;
• said DTC comprising a direct memory access means, coupled to said Local bus, including at least one direct memory access channel means, for channelling direct memory access transfers from said Local bus to said Remote bus and from said Remote bus to said Local bus;
• input/output controller means, coupled to said Local bus and to said Remote bus, including at least one address mapped input/output port means, for providing direct access to said second set of devices by said processor unit;
• means for connecting said Local bus to said direct memory access means and to said input/output controller means;
• and packing and funneling network means for interconnecting said Remote bus to said direct memory access means and said input/output controller means to accommodate variable width data transfers between said Local Bus and said Remote bus;
• wherein said DTC facilitates communication between said first and second sets of devices while insulating the performance of said first set of devices from the lower performance of said second set of devices and permits data transfer operations to be performed by said direct memory access means and said input/output controller means in parallel with the operation of said first set of devices.