Method and apparatus for testing and configuring the width of portions of a memory

A process for testing and configuring a width of various portions of a memory in a circuit having an address decoder for generating a memory control signal, a latch coupled to said address decoder for retaining a state of said memory control signal, and a control/test register coupled to said latch for receiving the state of said memory control signal retained by said latch, said control/test register being readable by a processor, said process comprising the steps of:

• providing an address and a memory width signal indicating a memory width to said address decoder, said memory width being the width of a corresponding portion of memory, said portion including a memory location specified by said address;
• latching said memory control signal generated by said address decoder, said latching step being performed by said latch when a valid address is provided to said address decoder;
• and
• reading the state of said memory control signal latched in said latching step.

A means for testing and configuring a width of various portions of a memory in a circuit having an address decoder for generating a memory control signal, a latch coupled to said address decoder for retaining a state of said memory control signal, and a control/test register coupled to said latch for receiving the state of said memory control signal retained by said latch, said control/test register being readable by a processor, said means for testing and configuring comprising:

• means for providing an address and a memory width signal indicating a memory width to said address decoder, said memory width being the width of a corresponding portion of memory, said portion including a memory location specified by said address;
• means for latching said memory control signal generated by said address decoder when a valid address is provided to said address decoder;
• and
• means for reading the state of said memory control signal latched by said means for latching.