Structure and method for monitoring an internal cache
AssigneeIntegrated Device Technology, Inc.
InventorsPhilip A. Bourekas, Yeshayahu Mor, Scott Revak
Life of this patent
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Abstract
A structure and a method are provided to bring internal signals of an integrated circuit to the external pins for monitoring purpose. In one embodiment, the signals on an internal bus between an on-chip cache and a CPU in a microprocessor are provided on the microprocessor's pins for a bidirectional data/address bus, when the bidirectional data/address bus is not used for data/address bus transactions with the main memory or the peripheral input/output devices. In this embodiment, reserved pins are used to selectively enable the address/data bus for bringing out the signals of the on-chip bus.
Claims14
A structure for monitoring internal signals of a microprocessor having a plurality of pins for outputting data signals, said structure comprising:
- a first circuit for receiving an external control signal having an active state, said active state indicating monitoring of said internal signals is desired;
- a second circuit, coupled to receive said external control signal, for providing said internal signals to said pins in response to said external control signal;
- and
- a third circuit for indicating that said internal signals are provided on said output pins, said third circuit providing an indicating signal on a control signal pin, said indicating signal indicating, when said external control signal is in said active state, whether internal signals or data signals are provided on said plurality of pins.
A method for monitoring internal signals of a microprocessor having a plurality of pins for providing, under control of a processing unit of said microprocessor output signals of said microprocessor, comprising:
- receiving an external control signal at an input pin of said integrated circuit indicating monitoring of said internal signals is desired;
- and
- when (i) said external signal is asserted and (ii) said output signals of said microprocessor are not provided on said plurality of pins:
- providing said internal signals to said plurality of pins;
- and indicating that said internal signals are provided on said plurality of pins.
An integrated circuit comprising:
- a processing unit;
- a plurality of pins for connection to an external circuit having a test instrument and a functional device, wherein said plurality of pins are provided with output signals for communication with said functional device;
- an internal bus that carries internal bus signals;
- a decoding circuit responsive to a test signal from said test instrument indicating monitoring of said internal bus signals is desired;
- and
- a bus interface that connects said internal bus to said plurality of pins, said bus interface comprising a multiplexor that selects said internal bus signal s to said pins when said pins are not being provided with said output signals.
Dependencies are inferred from the claim text.