Back to results
US 5,317,709 AGranted
Microcomputer including memory controller for DRAM
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorMasaki Sugimoto
Life of this patent
Estimating the term…
Abstract
There is provided a microcomputer including therein a DRAM controller, the DRAM controller including a refresh controller for refreshing a DRAM and an access controller for controlling the access to the DRAM whereby the need of a DRAM controlling external circuit that suffers from severe timing adjustment is eliminated and hence the DRAM is made directly connectable to the microcomputer.
Claims8
A memory controller for a memory comprising:
- a refresh controller coupled to the memory for issuing a plurality of signals to control memory refresh;
- an access controller coupled to the memory for controlling memory access and having:
- (a) a memory control register including:
- (i) a memory area selection bit for designating a given memory area;
- and
- (ii) a memory access effective bit, wherein when said memory access effective bit is asserted, access to the given memory area designated by said memory area selection bit is enabled;
- (b) an access signal generator circuit, coupled to said memory control register, for generating row and column addresses and RAS and CAS signals when said effective bit is asserted;
- and
- a bus arbiter, coupled to said memory, to said access controller and to said refresh controller, for assigning a priority to one of a refresh request or an access request to said given memory area.
6 more elements
A computer system comprising:
- at least one memory;
- a microcomputer having:
- (a) a CPU coupled to an internal bus;
- (b) a refresh controller, coupled to the internal bus and to said memory, for issuing a plurality of signals to control memory refresh;
- (c) an access controller coupled to the internal bus and to said memory for controlling memory access and having:
- (i) a memory control register including a memory area selection bit for designating a given memory area;
- and a memory access effective bit, wherein when said memory access effective bit is asserted, access to the given memory area designated by said memory area selection bit is enabled;
- (ii) an access signal generator circuit, coupled to said memory control register, for generating row and column addresses and RAS and CAS signals when said effective bit is asserted;
- and
- (d) a bus arbiter, coupled to said memory, to said access controller and to said refresh controller, for assigning a priority to one of a refresh request or an access request to said given memory area.
7 more elements
Dependencies are inferred from the claim text.