US 5,317,706 AGranted

Memory expansion method and apparatus in a virtual memory system

AssigneeNCR Corporation

InventorRichard G. Pechter

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Abstract

An apparatus for extending the memory of an electronic data processing system and a method for providing access to the extended memory for reading data, writing data, and refreshing data. The method provides a partitioning of the original virtual address space into a reduced virtual address space and an extended real memory address space. An extended address register is loaded initially with an extended memory control word by the operating system, but this word may not be changed again until the current process is over. If this control word is changed, it is changed by the operating system such that the use of the extended memory is transparent to the application processes using the system. The method further provides for refreshing of the memory circuitry of the extended memory. The apparatus supports the extended real memory address space by decoding the read and write accesses to the extended real address space, and by providing electrical connections for the refreshing of the extended memory circuitry. Thus, with this apparatus and method, the real memory of an electronic data processing system may be multiplied by a factor of two, four, or some higher multiple of two.

Claims10

Dependent claims

A memory expansion apparatus for a system having an extended main memory, said apparatus comprising:

a processor accessing an address location in extended main memory, said processor is connected to an address-and-data bus, and to a control bus;
a processor bus interface is also connected to said address-and-data bus, said processor bus interface also is connected to a non-extended address bus, and a data bus, said processor bus interface receives a first plurality of address bits from said processor, corresponding to the address location in extended memory which first plurality of address bits is outputted to said non-extended address bus;
external register means for storing an extended address control word connected to said processor bus interface via said non-extended address bus at an address input port, and to said data bus at a data input/output port of said external register means;
extended address selector means connected to said external register means for selecting a plurality of extended address bits from said extended address control word according to the extended address location in extended memory being accessed by said processor, said plurality of extended address bits are outputted from said extended address selector means to an extended address bus;
memory interface means, connected to said non-extended address bus, said data bus, and said extended address bus, for receiving said first plurality of address bits and said extended address bits, concatenating said extended address bits and said first plurality of address bits, and accessing said extended address location in said extended main memory;
said extended main memory is of a dynamic random access type that requires periodic refreshing in order to maintain digital information stored therein;
and
extended counter means for providing an extended refresh address for refreshing said extended main memory, said counter means is connected to said processor by a second control bus.

5 more elements

An apparatus to address an extended real memory location in a virtual memory system having an extended real memory, said apparatus comprising:

a processor for processing a virtual address connected to an address-and-data bus;
said processor having a memory management means for translating said virtual address to real address bits;
a processor bus interface is also connected to said address-and-data bus for communicating time division multiplexed address and data bits with said processor over said address-and-data bus;
said processor interface connected to an address bus, a data bus, and a control bus;
external register means for storing an extended address control word from said data bus, said external register means is connected to said address bus at an address input port, to said data bus at a data input/output port, and to an extended address output bus;
extended address selector means connected to said processor via a second control bus and to said external register means via said extended address output bus for selecting a plurality of extended address bits from said extended address control word according to said virtual address;
said plurality of extended address bits connected to an extended address bus;
and
memory interface means, connected to said address bus, said data bus, and said extended address bus, for accessing an extended address location in the extended real memory corresponding to said virtual address.

6 more elements

Dependencies are inferred from the claim text.