US 5,317,703 AGranted

Information processing apparatus using an advanced pipeline control method

AssigneeHitachi, Ltd.

InventorsTooru Hiraoka, Kouji Nakamura, Tohru Shonai

Life of this patent

Estimating the term…

Loading patent…

Abstract

An information processing method and apparatus for applying pipeline control and an advanced control to a sequence of instructions to be executed. The instruction sequence contains a plurality of conditional branch instructions. The apparatus includes a section for sequentially holding therein each instruction of the sequence of instructions to be input in a manner like a pipeline operation; an arithmetic section for obtaining a result of an operation of an instruction associated with each of the plural conditional branch instructions of the instruction sequence and selecting, from the associated instruction, instructions for which an advanced operation is possible so as to attain an operation result for each of the instructions thus selected; a holding section for holding therein either one of the operation result attained for each of the associated instructions and the operation result obtained in advance and outputting, at an execution of an objective conditional branch instruction selected from the plural conditional branch instruction; the operation result of a particular instruction corresponding to the objective conditional branch instruction, and a judge section for comparing branch control information of the objective conditional branch instruction with the operation result outputted from the holding means to judge a branch success or failure for the objective conditional branch instruction so as to decide a next instruction to be executed in accordance with the objective conditional branch instruction.

Claims10

Dependent claims

An information processing apparatus having a memory in which a pipeline control is applied to a sequence of instructions to be executed, the sequence of instructions including a plurality of conditional branch instructions, each of which determines whether a branch is successful or not based on a condition code obtained from a previously executed instruction, said apparatus comprising:

instruction providing meand for sequentially providing each individual instruction of the sequence of instructions to effect a pipeline operation thereon, wherein the instruction proividing means provides instructions, which occur in said sequence subsequent to a conditional branch instruction, before determining whether the branch is successful or not;
computing means for obtaining a first condition code by executing a first type of conditional branch instruction which is capable of execution without a memory address thereof, and for obtaining the memory address for a second type of instruction which requires the memory address information for execution;
arithmetic means for receiving, from the memory, advance operation data specified by a memory address obtained by the computing means, and for obtaining a second condition code resulting from the execution of the second type of instruction using the received advance operation data;
holding means responsive to said computing means and said arithmetic means for holding therein both of the first and second condition codes, wherein the holding means includes means for selecting the second condition code resulting from the execution of the second type of instruction before determining whether an objective conditional branch specified by that conditional branch instruction is successful or not;
and
determining means for comparing branch control information of the objective condition branch instruction with the selected second condition code output from the holding means, and for determining whether the objective conditional branch instruction is successful or not.

3 more elements

A method for use in an information processing apparatus for executing a sequence of instructions including a plurality of conditional branch instructions under a pipeline control and an advanced control, said method comprising the steps of:

sequentially holding each instruction of the sequence of instructions in a pipeline operation;
obtaining a first condition code by executing a first type of conditional branch instruction which is capable of execution without a memory address thereof, and for obtaining the memory address for a second type of conditional branch instruction which requires the memory address information for execution;
receiving, from the memory, advance operation data specified by a memory address obtained by the computing means, and for obtaining a second condition code resulting from the execution of the second type of instruction using the received advance operation data;
holding either one of the first condition code and the second condition code;
selecting, at an execution of an objective conditional branch instruction selected from the plural conditional branch instructions, a condition code resulting from the execution of a particular instruction corresponding to the objective conditional branch instruction;
comparing branch control information of the objective conditional branch instruction with the selected condition code;
determining a branch success or failure of the objective conditional branch instruction;
and
determining a next instruction to be executed in accordance with the objective conditional branch instruction.

6 more elements

Dependencies are inferred from the claim text.