Program history for pipelined processor including temporary storage queues for storing branch addresses

In a pipeline data processing system comprising processor means that execute branch-type instructions, program control means and a random access memory (RAM) coupled to said processor means and to said program control means for sorting processing function data for processes that are performable by said processor means, the improvement comprising a program history processing means which comprises:

• (a) first queue temporary storage means coupled to said processor means and to said program control means for storing the absolute "to" address program history data to which a branch instruction will jump,
• (b) second queue temporary storage means coupled to said processor means and to said program control means for storing the relative "to" address program history data to which the branch instruction will jump,
• (c) third queue temporary storage means coupled to said processor means and to said program control means for storing the relative "from" address program history data from which the branch instruction will jump,
• (d) queue multiplexing means coupled to said RAM and to said first, second and third queue temporary storage means for transferring said program history data stored in said queue temporary storage means to said RAM in a first-in-first-out manner for storage in said RAM at program history addresses that are specified by said program control means, and for receiving said processing function data for storage in said RAM as processing function addresses,
• (e) address multiplexing means coupled to said RAM and to said program control means for receiving said program history addresses and said processing function addresses, and
• (f) RAM means comprising write means coupled to said processor means, and to said program control means and to said queue and address multiplexing means for controlling the writing of said program history data and said processing function data into said RAM at controlled times that are determined by said processor means and said program control means, whereby said first, second and third queue temporary storage means allow the storage of the program history in said RAM means without interference with the use of said RAM means by the other functions that access it and without interference with the pipelining of said processor means.