Base-band delayed detector with synchronizing circuit
AssigneeFujitsu Limited
InventorsMasahiro Onoda, Yoshifumi Toda
Life of this patent
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Abstract
A base-band delayed detector has an operation circuit for performing a delayed detecting operation with respect to an input signal, the operation circuit outputting an altered signal having a predetermined symbol rate. The base-band delayed detector includes a clock generator for generating a clock signal having a frequency twice as large as the symbol rate, the clock signal being used as a timing signal in the operation circuit, a synchronizing circuit for synchronizing the clock signal with the altered signal output from the operation circuit and a data determination circuit for obtaining output data from the altered signal at a predetermined timing based on the clock signal synchronized with the altered signal.
Claims10
A base-band delayed detector receiving an input signal and having operation means performing, in synchronism with a clock signal, a delayed detecting operation on the input signal, said operation means outputting an altered signal having a predetermined symbol rate, said base-band delayed detector comprising:
- clock generation means for generating a clock signal having a frequency 2.times.n times as high as the predetermined symbol rate, said clock signal being used as a timing signal for said operation means, where n is an integer;
- dividing means for dividing said frequency of said clock signal, generating a divided signal;
- inverting means for inverting said divided signal, generating an inverted signal;
- detection means for detecting a pattern of polarities of said altered signal at predetermined timings defined by said divided signal and said inverted signal;
- determining means for making a determination whether a phase of said clock signal one of lags and precedes a phase of said altered signal based on said pattern of polarities detected by said detection means;
- shifting means for shifting the phase of the clock signal based upon said determination in order to synchronize said clock signal with said altered signal;
- and
- data determination means for identifying a synchronized state when said altered signal is synchronized with said clock signal, and outputting said altered signal during said synchronized state.
A base-band delayed detector receiving an input signal and having operation means performing, in synchronism with a clock signal, a delayed detecting operation on the input signal, said operation means outputting an altered signal having a predetermined symbol rate, said base-band delayed detector comprising:
- clock generation means for generating a clock signal having a frequency 2 times as high as the predetermined symbol rate, said clock signal being used as a timing signal for said operation means;
- first generation means for generating a first clock signal based on said clock signal generated by said clock generation means, said first clock signal having a frequency half that of said clock signal;
- second generation means for generating a second clock signal based on said clock signal generated by said clock generation means, said second clock signal having a frequency half that of said clock signal and being in an inverted state relative to said first clock signal;
- first sampling means for sampling a first polarity of said altered signal output from said operation means in synchronism with said first clock signal;
- second sampling means for sampling a second polarity of said altered signal output from said operation means in synchronism with said second clock signal;
- means for making a determination whether a phase of said clock signal one of lags and precedes a phase of said altered signal based on an arrangement of said first and second polarities respectively sampled by said first and second sampling means;
- shifting means for shifting the phase of the clock signal based upon said determination in order to synchronize said clock signal with said altered signal;
- and
- data determination means for identifying a synchronized state when said altered signal is synchronized with said clock signal, and outputting said altered signal during said synchronized state.
Dependencies are inferred from the claim text.