US 5,317,572 AGranted

Hybrid multiplex synchronizing method and apparatus therefor

AssigneeFujitsu Limited

InventorJunichi Satoh

Life of this patent

Estimating the term…

Loading patent…

Abstract

Disclosed are a hybrid multiplex synchronizing method and apparatus therefor, in which, when time-shared multiplexed data having different frame patterns and different frame lengths are inputted in different phases every time slot, the data are transmitted upon making the phases of the data in each time slot identical. The apparatus stores in advance, in correlation with the time slots, types of frame patterns and frame lengths of time-shared multiplexed data allocated to each time slot, and performs frame-pattern detection processing in correspondence with each of the different frame patterns. A synchronized-phase detection signal is output in response to detection of the frame pattern, and when the synchronized-phase detection signal is generated in response to detection of the frame pattern of the time-shared multiplexed data allocated to each time slot, the time-shared multiplexed data in the each time slot is rearranged in memory, taking into consideration the frame length of these data, based upon the synchronized-phase detection signal. The phases of the data in each of the time slots are then identical to one another.

Claims11

Dependent claims

A hybrid multiplex synchronizing method in a data multiplex communication apparatus having multiplex synchronizing processors in which, when time-shared multiplexed data having prescribed frame patterns, some of which are different than others, are inputted in different phases every time slot, said multiplex synchronizing processors perform detection processing to detect frame patterns of time-shared multiplexed data allocated to said time slots and output synchronized-phase detection signals in response to detection of the frame patterns, and a phase synchronizer for rearranging the time-shared multiplexed data of each time slot in memory based upon the synchronized-phase detection signals and making the phases of the time-shared multiplexed data identical, said method comprising the steps of:

storing in advance, in correlation with time slots, information as to the types of frame patterns and frame lengths of time-shared multiplexed data allocated to each time slot, in a case where plural items of time-shared multiplexed data having different frame patterns and different frame lengths are processed;
providing multiplex synchronizing processors designated for respective ones of the frame patterns, performing frame-pattern detection processing in each of the multiplex synchronizing processors whenever a frame bit identifying one of the frame patterns is inputted, and outputting a synchronized-phase detection signal in response to detection of the frame pattern;
and
when the synchronized-phase detection signal is generated by a multiplex synchronizing processor conforming to the type of frame pattern which corresponds to a present time slot, as determined from the stored information, having said phase synchronizer rearrange the time-shared multiplexed data in the present time slot in memory, upon taking into consideration the frame length of these data, based upon the synchronized-phase detection signal, and similarly rearrange the time-shared multiplexed data of each time slot in memory to make the phases of the time-shared multiplexed data of the time slots identical to one another.

1 more element

A hybrid multiplex synchronizing apparatus in which, when time-shared multiplexed data having prescribed frame patterns and different frame lengths, some of which are different than others, are inputted in different phases every time slot, the data are transmitted upon making the phases of the time-shared multiplexed data in each time slot identical, comprising:

a memory for storing in advance, in correlation with time slots, information as to the types of frame patterns and frame lengths of the time-shared multiplexed data allocated to each time slot;
multiplex synchronizing processes designated for respective ones of different frame patterns for performing, for every time slot, frame-pattern detection of the time-shared multiplexed data allocated to said time slot, and outputting a synchronized-phase detection signal in response to detection of the frame pattern;
a frame aligning RAM having m-number of storage areas which are first, second, . . . , m-th storage areas for every time slot, where m represents maximum frame length;
a selector for selecting and outputting the synchronized-phase detection signal generated by a multiplex synchronizing processor conforming to the type of frame pattern which corresponds to a present time slot, as determined from the information stored in said memory;
and
a phase synchronizer which, on the basis of the synchronized-phase detection signal generated every time slot, stores the time-shared multiplexed data of each time slot in the corresponding m-number of storage areas of said frame aligning RAM in order, starting from the first storage area, upon taking into consideration the frame length, based upon the synchronized-phase detection signal, and makes the phases of the items of time-shared multiplexed data of the time slots identical to one another.

3 more elements

Dependencies are inferred from the claim text.