Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorTohru Furuyama
Life of this patent
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Abstract
A semiconductor memory device comprises a memory cell array in which cascade-gate dynamic memory cells are arranged in a matrix and which contains word lines connected in common to the memory cells in the same row and bit lines connected in common to the memory cells in the same column, and serial access control means which serially accesses a plurality of memory cells in a given column of the memory cell array, reads a plurality of bits of information in time-sequence from one of the memory cells storing information, and then sequentially rewrites the bits of information into a different memory cell unused for storing valid data, in the same column where the memory cell exists.
Claims53
A semiconductor memory device, comprising:
- a memory cell array in which cascade dynamic memory cell units each capable of storing a plurality of bits of information in bits are arranged in a matrix, the memory cells in the same row being connected in common to a corresponding one of a plurality of word lines and the memory cell units in the same column being connected in common to a corresponding one of a plurality of bit lines;
- and
- serial access control means which serially accesses a plurality of memory cell units in a given column of said memory cell array, reads a plurality of bits of information in time-sequence from one of the memory cell units storing information through one of said bit lines connected to the one of said memory cell units, and then sequentially rewrites the bits of information into a different memory cell unit of the memory cell array unused for storing valid data, in the same column containing said one memory cell unit.
A semiconductor memory device, comprising:
- bit lines;
- circuit units each connected to a corresponding one of said bit lines, each circuit unit connected to the corresponding bit line at respective first and second data nodes and comprising:
- at least three transistors connected in series between said first and second data nodes such that a first terminal of a first transistor in said series is connected to said first data node, a second terminal of a last transistor in said series is connected to said second data node, and a first terminal of each remaining transistor in said series is connected to a second terminal of the immediately preceding transistor in said series;
- and
- a plurality of data storage capacitors, each data storage capacitor having a first terminal connected to the second terminal of one of said transistors except said last transistor in said series;
- word lines connected to control terminals of said transistors;
- and
- access control circuitry connected to said word lines for reading a data item from a first data storage capacitor of a first circuit unit having valid data items at an access time and writing said data item to a first data storage capacitor of a second circuit unit not having valid data items at said access time.
A semiconductor memory device, comprising:
- a bit line;
- circuit units connected to said bit line, each circuit unit connected to said bit line at respective first nodes and comprising:
- at least two transistors connected in series such that a first terminal of a first transistor in said series is connected to said first data node and a first terminal of each remaining transistor in said series is connected to a second terminal of the immediately preceding transistor in said series;
- and
- data storage capacitors each having a first terminal connected to the second terminal of one of said transistors;
- word lines connected to control terminals of said transistors;
- and
- access control circuitry coupled to said word lines for reading a first data item from a first data storage capacitor of a first circuit unit having valid data items at an access time and writing said first data item to a first data storage capacitor of a second circuit unit not having valid data items at said access time.
Dependencies are inferred from the claim text.