Low power DRAM
AssigneeUnited Memories, Inc.
InventorS. Sheffield Eaton, Jr.
Life of this patent
Estimating the term…
Abstract
In a DRAM, a logic "1" is redefined as the minimum VCC value minus one threshold voltage. The word line is not bootstrapped. This intermediate voltage is applied via the sense amplifier to the bit lines during refresh. The intermediate value is controlled preferably by a comparator controlling a driver. Even when the power supply voltage rises, the intermediate voltage is held constant by comparison to a fixed reference voltage. Operating current is substantially reduced because less power is required to write data into the memory cells, since a controlled lower voltage is used.
Claims17
A method of decreasing power consumption in an integrated circuit DRAM having a specified minimum power supply voltage, and wherein transistors in said DRAM have threshold voltages, the DRAM having memory cells associated with bit lines to which voltages are applied during read and refresh operations, the method comprising:
- limiting the bit line voltages for said read and refresh operations substantially to a value no higher than the minimum specified power supply voltage minus one said threshold voltage, said limiting step including
- comparing a reference signal to a drive signal applied to a sense amplifier coupled to one or more bit lines of the DRAM, and
- controlling the magnitude of the drive signal in response to said comparing step.
An integrated circuit DRAM having bit lines, memory cells, word lines, and a sense amplifier, wherein data is stored in a memory cell by a voltage stored on a storage capacitor in the memory cell,
- said DRAM further including a sense amplifier drive line coupled to the sense amplifier, a sense amplifier driver connected to provide a drive voltage to said sense amplifier drive line, and a drive line control circuit coupled to said sense amplifier driver;
- said control circuit being effective to provide a comparison function between a reference voltage and the drive voltage so that the drive voltage applied to the sense amplifier is controlled in accordance with the comparison, the bit line voltages during write and refresh operations being thereby controlled so that the voltage corresponding to one datum is no greater than substantially a minimum specified power supply voltage minus one threshold voltage over the normal operating range of the DRAM.
An integrated circuit DRAM of the type including a sense amplifier coupled to a bit line, a word line, a memory cell disposed at or near the intersection of the word line and the bit line, wherein the improvement comprises:
- means for generating a non-zero voltage lower than a power supply voltage ("VCC"), said means for generating including an input for receiving a reference signal substantially independent of the value of VCC;
- and
- means for applying said voltage to the bit lines for restoring or writing a datum value into the memory cell.
A method of operating a DRAM comprising the steps of:
- receiving a power supply voltage between a minimum value and a maximum value;
- and
- establishing a non-zero voltage lower than the minimum power supply voltage and writing no higher than said non-zero voltage as a logic "1",
- said establishing step including using a reference voltage to provide said non-zero voltage.
Dependencies are inferred from the claim text.