Multi-port memory device having precharged bit lines

A multi-port memory device comprising:

• a memory cell array including at least one memory block each having a plurality of memory cells arranged in rows and columns, said memory cells being connected with word lines extending in a row direction and with memory cell bit lines extending in a column direction;
• a plurality of dummy cells, one provided for each row of memory cells in each of said memory blocks so that the dummy cells are connected with associated ones of said word lines extending in the row direction, said dummy cells further being connected with dummy cell bit lines extending in the column direction;
• means for precharging said memory cell bit lines and dummy cell bit lines to a predetermined precharge voltage when said memory cell array is not subjected to a memory cell selection operation so that reading of information from a memory cell is effected in terms of a change of a voltage of a memory cell bit line from said predetermined precharge voltage with which the memory cell is connected, said dummy cells having a time constant larger than that of said memory cells;
• and
• sense amplifier means connected to receive first discharge signals from memory cell bit lines connected with those memory cells in said memory cell array which are selected in a memory cell selection operation and second discharge signals from dummy cell bit lines connected with those dummy cells among said plurality of dummy cells which are selected in said memory cell selection operation for amplifying differences between said first and second discharge signals and delivering the amplified differences as information read from said memory cell array.

A multi-port memory device having a plurality of memory cells, comprising:

• write bit lines each including complementary signal lines connected to writing terminals of the memory cells;
• read bit lines each including of a single-ended signal line connected to reading terminals of the memory cells;
• dummy bit lines connected to dummy cells and provided in correspondence to said read bit lines, respectively;
• and
• sense amplifiers of differential input type each having a non-inverted input terminal connected to a corresponding one of said read bit lines and an inverted input terminal connected to a corresponding one of said dummy bit lines.

A multi-port memory device comprising:

• write bit lines each including complementary signal lines;
• first and second read bit lines each including of a single-ended signal line;
• first and second dummy bit lines provided in correspondence to said read bit lines, respectively;
• and
• sense amplifiers of differential input type each having a non-inverted input terminal connected to a corresponding one of said read bit lines and an inverted input terminal connected to a corresponding one of said dummy bit lines;
• a write word line and said first and second read word lines provided in correspondence to each of row address,
• said write bit lines and the first and second read bit lines provided in correspondence to each of column addresses;
• and
• wherein said multi-port memory device includes a plurality of static type memory cells, each of said memory cells comprising:
• a latch circuit including first and second CMOS inverters cross-coupled to each other,
• said latch circuits included in said plurality of static type memory cells, respectively, being disposed in rows and columns at cross-points between said write word lines and said first and second read word lines on one hand and said write bit lines and said first and second read bit lines on the other hand;
• wherein each of said latch circuits has first non-inverted and inverted input/output nodes coupled to the corresponding ones of said write bit lines through a pair of write control MOSFETs having gates coupled to corresponding ones of said write word lines, said latch circuit having second non-inverted and inverted input/output nodes which are coupled to corresponding ones of said first and second read bit lines through first and second read control MOSFETs having a gate coupled to a corresponding one of said first or second read word lines.