Apparatus for reducing the size of an arithmetic and logic unit necessary to practice non-restore division

A circuit for accomplishing arithmetic operations comprising:

• an arithmetic and logic unit (ALU);
• a first register for holding a dividend to be divided and intermediate and final results of a division operation;
• a second register for holding a divisor;
• a logic circuit for controlling the ALU to practice the operation of non-restore division by sequentially causing bits of the dividend to be shifted by one bit toward the highest order bit position and the divisor to be subtracted from or added to the highest order bits of the dividend and interim dividends in order to sequentially subtract and add the dividend and the divisor,
• a third register for storing apart from the arithmetic and logic unit a value of a highest order bit of a dividend in the first register;
• and
• an exclusive NOR (XNOR) circuit connected to receive as input values a carryout of any operation of the ALU and the value of the highest order bit of the dividend stored in the third register;
• an output of the XNOR circuit being connected to provide input during a division operation to the least significant bit position of the first register and to provide a signal to control the particular sequential operation performed by the ALU.

A circuit for carrying out division of binary numbers in which an unsigned dividend is of a maximum bit length, comprising:

• an arithmetic and logic unit (ALU) having a number of bit positions equal to a maximum bit length of an unsigned dividend,
• a dividend register having a number of bit positions equal to the maximum bit length of an unsigned dividend, the dividend register being connected to provide input to the ALU and to receive output therefrom,
• a divisor register connected to provide input to the ALU and having a number of bit position equal to one-half the maximum bit length of an unsigned dividend,
• a logic circuit for controlling the ALU to divide a dividend by a divisor utilizing a non-restore process having a number of iterations each of which includes a shift toward the highest order bit and either a subtraction or an addition of the divisor from the highest order bits remaining,
• a counter circuit for controlling the number of iterations of the logic circuit during a division operation,
• a most significant bit register positioned apart from the ALU and connected to receive a highest order bit held by the dividend register, and
• a logical exclusive NOR (XNOR) circuit connected to receive as input a value stored in the most significant bit register and any carryout value from a subtraction or addition iteration of a division operation,
• the XNOR circuit being connected to provide an output signal to the ALU to control the next step of a division operation to be a subtraction if the output is a one value or an addition if the output is a zero value,
• the XNOR circuit being connected to provide an output signal to a lowest bit position of the dividend register during each step of a division operation.