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US 5,317,530 AGranted
Rounding operation circuit
AssigneeNEC Corporation
InventorYoshitaka Toriumi
Life of this patent
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AssigneeNEC Corporation
InventorYoshitaka Toriumi
Estimating the term…
A rounding operation circuit for arithmetic logic unit of a signal processor provided for counting fractions over 1/2 as one and disregarding the rest for the positive and negative number, which comprises a decoder circuit having an (n+1)-long input to which a first input signal represented by two's complement and a second n-bit long input signal for specifying the rounded position of the first signal are entered, when the first input signal is positive, a signal in which the bit at the rounded position is "1" and the rest is "0" is emitted based on the second input signal and, when the first input signal is negative, a signal in which the bits less significant than the bit at the rounded position are all "1" and the rest is "0" is emitted; arithmetic logic unit for adding the output signal of this decoder circuit and the first input signal; and a rounding circuit for counting 1 and cutting away 0 positively and negatively symmetrically to any rounding position, to allow a fast and accurate rounding operation.
A rounding operation circuit for performing a rounding operation on a first input signal represented in a two's complement form, comprising decoder means for receiving a second input signal designating a rounding position of said first input signal and for outputting a decoded signal in which a bit corresponding to said rounding position takes logic "1" and remaining bits take logic "0" when said first input signal is positive and in which a bit or bits less significant that said bit corresponding to said rounding position takes logic "1" and remaining bit or bits take logic "0" when said first input signal is negative;
A rounding circuit for rounding input data (1) represented in a two's complement form to produce rounded data, comprising a decoder supplied with control data indicative of a rounding position of said input data and outputting first decoded data when said input data is positive and second decoded data when said input data is negative, said first decoded data consisting of a bit that takes a first logic level and corresponds to said rounding position and remaining bits that take a second logic level, said second decoded data consisting of a bit or bits that take said first logic level and are less significant than said bit corresponding to said rounding position and remaining bit or bits that take said second logic level, and operational unit adding said input data with the decoded data derived from said decoder and outputting added data, and a rounding-down circuit producing said rounded data to said added data and said control data, said rounded data having a bit or bits that are less significant than a bit corresponding to said rounding position and rounded down to said second logic level.
Dependencies are inferred from the claim text.