US 5,317,219 A · Compensated digital delay circuit

Abstract

A programmable compensated digital delay circuit is described in a design format that is suited for integrated circuitry utilizing complementary MOS technology. In the integrated circuit delay, a precise single element is provided that spans a wide delay range. The element has multiple time delay cells that are selectively interconnectable to form one or more delay lines. Each time delay cell has controllable capacitive elements and current sources which, in turn, are selected by use of a nonvolatile memory. Both the capacitive elements and the current sources are arrayed in a binary weighted manner. The delay is set by using portions of the memory to select capacitive elements and current sources. With the memory functioning with other integrated circuitry, different capacitive elements and current sources are switched into and out of the circuit. The programmable compensated digital delay circuit of the invention is self-compensating for temperature and power supply variations. The compensation adjusts the operating levels and subranges of the time delay lines. A precision delay line is formed from complementary MOS technology without using a reference frequency. The precision delay line is further characterized by high pulse fidelity that is, one with substantially no pulse width distortion and by high operating frequency.

Claims19

Dependent claims

A compensated digital delay circuit having a design format suited for integrated circuitry utilizing complementary MOS technology comprising:

an input for signals-to-be-delayed;
a delay line with a plurality of time delay cells connected to said input, each of said time delay cells selectively interconnectable for forming one or more delay configurations, said delay line having a first output therefrom;
first circuit means for generating a variable current from a control voltage, said first circuit means connected to said time delay cells;
internal compensation means for compensating temperature and power supply variations, said internal compensation means connected to said first circuit means to adjust the time delay of the delay cells, said internal compensation means, in turn, comprising:
ring oscillator means for temperature and power supply compensation, said oscillator means having time delay cells selected for interchangeability with those of said delay line, said first output of said delay line connected to the ring oscillator, said ring oscillator having a second output therefrom;
second circuit means for generating a variable current from a reference voltage, said second circuit means connected to said ring oscillator;
and,
control circuit means for generating a variable voltage signals for connection to said first circuit means to adjust the current to the time delay cells, said control circuit means connected to said second output of said ring oscillator;
whereby a precision delay line is formed from complementary MOS technology employing an oscillator means to compensate for temperature and power supply variations and without using a reference frequency for timing.

6 more elements

A compensated digital delay circuit having a design format suited for integrated circuitry with components deposited thereon by complementary MOS technology comprising:

a first input for signals-to-be-delayed;
a delay line connected to said first input with a plurality of time delay cells selectively interconnectable, for forming one or more delay lines, each of said time delay cell having a first plurality of controllably selectable circuit components, including capacitive elements and current sources, said delay line having a first memory input means for programmably selecting circuit components;
first circuit means for generating a variable current from a control voltage, said first circuit means connected to said time delay cells;
ring oscillator means for temperature and power supply compensation, said oscillator means formed from a second plurality of time delay cells selected for interchangeability with said plurality of time delay cells, each oscillator means having identically selected capacitive elements and current sources as the corresponding delay line, said ring oscillator having a second memory input means for programmably selecting circuit components;
a non-volatile memory for selecting one or more said components within said integrated circuitry, said memory operative to switch said components into and out of the programmable compensated digital delay circuit, said non-volatile memory connected to said first memory input means of said delay line and to said second memory input means of said ring oscillator;
a second input for receiving said reference voltage, said second input connected to said ring oscillator;
and,
error voltage circuit means for generating an error voltage signal, said error voltage circuit means connected to said first circuit means for adjustment of the control voltage to the programmable compensated digital delay circuit;
whereby a precision delay line is formed from complementary MOS technology without using a reference frequency for timing.

6 more elements

Dependencies are inferred from the claim text.

Compensated digital delay circuit

Life of this patent

Compensated digital delay circuit

Life of this patent

Abstract

Claims19