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US 5,317,213 AGranted

Level converter with delay circuitry used to increase switching speed

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsHirotoshi Sato, Atsushi Ohba, Akira Hosogane

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Abstract

A level converting circuit has a function of converting an input signal of a first logic level into an output signal of a second logic level. The level converting circuit includes a first transistor responsive to an input signal IN for charging an output node to the ground potential, a second transistor responsive to the input signal IN for lowering the potential of the output node to the negative potential VEE, a third transistor responsive to the potential of the output node for controlling operations of the second transistor, and fourth and fifth transistors responsive to a delay signal with delay to an output of the level converting circuit for controlling the amount of current flowing through the output node. An inverted, amplified signal of the output node is applied to the gate of the fourth transistor, and a non-inverted, amplified signal of the output node is applied to the gate of the fifth transistor. The fourth and the fifth transistors serve to enhance the potential change of the output node by the delay signal (amplified signal). As a result, a level converting circuit carrying out a switching operation at a high speed in response to the input signal IN can be implemented.

Claims25

Dependent claims

Claim 1A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level · 157 wordsNo dependents Claim 2A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level · 157 wordsNo dependents Claim 3A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level · 284 words3 dependent Claim 7A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level · 313 words3 dependent Claim 11A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level · 197 words6 dependent Claim 18A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level · 271 words1 dependent Claim 20A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level · 460 words2 dependent Claim 23A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level · 437 words2 dependent

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising:

an output node for supplying the output signal;
first means responsive to said input signal for setting said output node at a level of a first potential;
second means responsive to said input signal for setting said output node at a level of a second potential;
delay means for delaying a signal at said output node;
and
control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential,
wherein said second means includes latch means for latching a signal potential at said output node, and wherein said control means includes means responsive to said delay signal, for changing the magnitude of a resistance between said latch means and said second potential.

4 more elements

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising:

an output node for supplying the output signal;
first means responsive to said input signal for setting said output node at a level of a first potential;
second means responsive to said input signal for setting said output node at a level of a second potential;
delay means for delaying a signal at said output node;
and
control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential,
wherein said second means includes latch means for latching a signal potential at said output node, and
wherein said control means includes means responsive to said delay signal, for changing the magnitude of a resistance between said output node and said latch means.

5 more elements

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising:

an output node for supplying the output signal;
first means responsive to said input signal for setting said output node at a level of a first potential;
second means responsive to said input signal for setting said output node at a level of a second potential;
delay means for delaying a signal at said output node;
and
control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential,
wherein said second means includes:
a first field effect transistor provided between said input node and a first node having a gate receiving a predetermined reference potential,
a second field effect transistor having one conduction terminal coupled to receive said second potential and a gate connected to said output node,
a third field effect transistor having one conduction terminal coupled to receive said second potential and a gate connected to said first node, and
wherein said delay means includes:
a first buffer for inverting and amplifying a signal at said output node, and a second buffer for inverting and amplifying an output signal of said first buffer,
and wherein said control means includes:
a fourth field effect transistor provided between said first node and said second field effect transistor and having a gate receiving the output signal of said first buffer, and
a fifth field effect transistor provided between said output node and said third field effect transistor and having a gate receiving an output signal of said second buffer.

12 more elements

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising:

an output node for supplying the output signal;
first means responsive to said input signal for setting said output node at a level of a first potential;
second means responsive to said input signal for setting said output node at a level of a second potential;
delay means for delaying a signal at said output node;
and
control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential,
wherein said second means includes:
a first field effect transistor having one conduction terminal connected to said input node, another conduction terminal connected to a first node, and a gate connected to receive a predetermined potential,
a second field effect transistor having one conduction terminal connected to said first node, another conduction terminal connected to a second node, and a gate connected to said output node, and
a third field effect transistor having one conduction terminal connected to said output node, another conduction terminal connected to a third node, and
wherein said delay means includes:
a first buffer for inverting and amplifying a signal at said output node, and
a second buffer for inverting and amplifying an output of said first buffer, and
wherein said control means includes:
a fourth field effect transistor having one conduction terminal connected to said second node, another conduction terminal connected to receive said second potential, and a gate connected to receive the output of said first buffer, and
a fifth field effect transistor having one conduction terminal connected to said third node, another conduction terminal connected to receive said second potential, and a gate connected to receive an output of said second buffer.

13 more elements

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising:

an output node for supplying the output signal;
first means responsive to said input signal for setting said output node at a level of a first potential;
second means responsive to said input signal for setting said output node at a level of a second potential;
delay means for delaying a signal at said output node;
and
control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential,
wherein said second means includes a first current path between said input node and a node supplying said second potential, for providing a current flow responsive to said input signal, and
a current path between said output node and the node supplying said second potential in a current mirror configuration with said first current path, and
wherein said control means includes:
means responsive to the delay signal for changing a resistance value of at least one of said first and second current paths.

7 more elements

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising:

an output node for supplying the output signal;
first means responsive to said input signal for setting said output node at a level of a first potential;
second means responsive to said input signal for setting said output node at a level of a second potential;
delay means for delaying a signal at said output node;
and
control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential,
wherein said second means includes:
a first field effect transistor responsive to an input signal complementary to the input signal applied to said first means for charging a first node at a level of the first potential,
a second field effect transistor having one conduction terminal connected to a second node, a gate connected to said first node, and another conduction terminal connected to receive a second potential, and
a third field effect transistor having one conduction terminal connected to said output node, a gate connected to said first node, and another conduction terminal connected to receive said second potential, and
wherein said delay means includes:
a first buffer for buffering a signal at said output node, and
wherein said control means includes:
a fourth field effect transistor having one conduction terminal connected to said first node, another conduction terminal connected to said second node, and a gate connected to receive an output of said buffer means.

11 more elements

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising:

an output node for supplying the output signal;
first means responsive to said input signal for setting said output node at a level of a first potential;
second means responsive to said input signal for setting said output node at a level of a second potential;
delay means for delaying a signal at said output node;
and
control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential,
wherein said first means includes:
a first field effect transistor responsive to a signal received at a first input node for charging a first output node to the first potential, and
a second field effect transistor responsive to a signal received at a second input node for charging a second output node to the first potential, the signal at the first input node being complementary to the signal at the second input node, and
wherein said second means includes:
a third field effect transistor responsive to the signal at the second input node for charging a first node to the first potential,
a fourth field effect transistor having one conduction terminal connected to a second node, a gate connected to said first node, and another conduction terminal connected to receive a second potential,
a fifth field effect transistor having one conduction terminal connected to said first output node, a gate connected to said said first node, and another conduction terminal connected to receive the second potential,
a sixth field effect transistor responsive to the signal at the first input node for charging a third node to the first potential,
a seventh field effect transistor having one conduction terminal connected to a fourth node, a gate connected to the third node, and another conduction terminal connected to receive the second potential, and
an eighth field effect transistor having one conduction terminal connected to the second output node, a gate connected to the third node, and another conduction terminal connected to receive the second potential, and
wherein said delay means includes:
a first buffer for buffering the signal at said first output node, and
wherein said control means includes:
a ninth field effect transistor having one conduction terminal connected to said first node, a gate connected to receive an output of said first buffer, and another conduction terminal connected to the second node, and
a tenth field effect transistor having one conduction terminal connected to the third node, a gate connected to receive an output of said second buffer, and another conduction terminal connected to the fourth node.

18 more elements

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising:

an output node for supplying the output signal;
first means responsive to said input signal for setting said output node at a level of a first potential;
second means responsive to said input signal for setting said output node at a level of a second potential;
delay means for delaying a signal at said output node;
and
control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential,
wherein said first means includes:
a first field effect transistor responsive to a signal received at a first output node, for charging a first output node to a level of the first potential, and
a second field effect transistor responsive to a signal at a second input node, for charging a second output node to a level of the first potential, the signal at the first input node being complementary to the signal at the second input node, and wherein said second means includes:
a third field effect transistor having one conduction terminal connected to the first output node, a gate connected to receive the signal at the first input node, and another conduction terminal connected to a first node,
a fourth field effect transistor having one conduction terminal connected to a second node, a gate connected to the second output node, and another conduction terminal connected to receive a second potential,
a fifth field effect transistor having one conduction terminal connected to the second output node, a gate connected to the second input node, and another conduction terminal connected to a third node, and
a sixth field effect transistor having one conduction terminal connected to a fourth node, a gate connected to the first output node, and another conduction terminal connected to receive the second potential and
wherein said delay means includes:
a first buffer for buffering the signal at said second output node, and
a second buffer for buffering the signal at said first output node, and
wherein said control means includes:
a seventh field effect transistor having one conduction terminal connected to a first node, a gate connected to receive an output of the second buffer, and another conduction terminal connected to the second node, and
an eighth field effect transistor having one conduction terminal connected to the third node, a gate connected to receive an output of the first buffer, and another conduction terminal connected to the fourth node.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/961,979Filed 16 Oct 1992
Priority: JP 3-30621421 Nov 1991
Granted: 31 May 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03K 3/356017
Bistable circuits: using additional transistors in the input circuit
H03K 3/356113
Using complementary field-effect transistors: using additional transistors in the input circuit
H03K 19/018521
Interface arrangements: of complementary type, e.g. CMOS
H03K
Pulse technique

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