Programmable pin for use in programmable logic devices

A circuit for programming an I/O site in a programmable logic device, comprising:

• a first multiplexor having first and second inputs, a select input and an output, said first input of said first multiplexor being coupled to receive a first signal, said second input of said first multiplexor being coupled to a first supply voltage terminal;
• a second multiplexor having first and second inputs, a select input and an output, said first input of said second multiplexor being coupled to receive a second signal, said second input of said second multiplexor being coupled to a second supply voltage terminal;
• a p-channel transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode of said p-channel transistor being coupled to the I/O site, said second current carrying electrode of said p-channel transistor being coupled to said first supply voltage terminal, said control electrode of said p-channel transistor being coupled to said output of said second multiplexor;
• an n-channel transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode of said n-channel transistor being coupled to the I/O site, said second current carrying electrode of said n-channel transistor being coupled to said second supply voltage terminal, said control electrode of said n-channel transistor being coupled to said output of said first multiplexor;
• circuit means being coupled to receive a driving signal, an enable signal and first and second control signals for providing said first and second signals respectively to said first inputs of said first and second multiplexors;
• and
• control means for providing a first select signal to said select inputs of said first and second multiplexors, said control means having inputs being responsive to first and second control signals, said control means having first and second outputs respectively coupled to said select inputs of said first and second multiplexors.

A circuit for programming an I/O site of a programmable logic device, comprising:

• a first multiplexor having first, second, third and fourth inputs, first and second select inputs, and an output, said third and fourth inputs of said first multiplexor being coupled to receive a signal, said second input of said first multiplexor being coupled to a first supply voltage terminal, said first input of said first multiplexor being coupled to a second supply voltage terminal, said first and second select inputs of said first multiplexor being respectively coupled to receive first and second control signals;
• a second multiplexor having first and second inputs, a select input and an output, said first input of said second multiplexor being coupled to said first supply voltage terminal, said second input of said second multiplexor being coupled to receive an enable signal, said select input of said second multiplexor being coupled to receive said first control signal;
• a tri-state logic circuit having first and second inputs and first and second outputs, said first and second inputs of said tri-state logic circuit being respectively coupled to said outputs of said first and second multiplexors;
• a p-channel transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode of said p-channel transistor being coupled to the I/O site, said second current carrying electrode of said p-channel transistor being coupled to said first supply voltage terminal, said gate electrode of said p-channel transistor being coupled to said first output of said tri-state logic circuit;
• and
• an n-channel transistor having first and second current carrying electrodes and a control electrode, said first current carrying electrode of said n-channel transistor being coupled to the I/O site, said second current carrying electrode of said n-channel transistor being coupled to said second supply voltage terminal, said control electrode of said n-channel transistor being coupled to said second output of said tri-state logic circuit.

A circuit for programming an I/O site in a programmable logic device, comprising:

• first multiplexor means being responsive to first and second select signals for providing either a signal, a first voltage or a second voltage at an output thereof;
• second multiplexor means being responsive to said first select signal for alternately providing an another signal or said second voltage at an output thereof;
• a tri-state logic circuit (46) having first and second inputs and first and second outputs, said first and second inputs of said tri-state logic circuit being respectively coupled to said outputs of said first and second multiplexor means;
• and
• an output transistor circuit being coupled between said first and second voltages and to the I/O site, said output transistor circuit having first and second inputs being respectively coupled to said first and second outputs of said tri-state logic circuit.