I/O cell for programmable logic device providing latched, unlatched, and fast inputs
AssigneeAltera Corporation
InventorRakesh H. Patel
Life of this patent
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Abstract
An input/output cell for interconnecting an I/O pad with internal circuitry in a programmable logic device provides clocked and unclocked inputs through an internal bus to selected logic array blocks. The input/output cell further includes a fast input line in which the I/O pad is directly connected with a selected logic array block without travelling through the latch circuitry of the I/O cell and the internal bus of the programmable logic device.
Claims9
An input/output (I/O) cell for interconnecting an I/O pad with an array of logic blocks in a programmable logic device in both a clocked and unclocked mode comprising
- a first multiplexing means having an input and a plurality of outputs, said first multiplexing means selectively connecting said input through one of said outputs to an array of logic array blocks through an internal bus of said PLD,
- latch means driven by a clock and coupled to said I/O pad and to said first multiplexing means for providing a clocked output to said I/O pad and clocked inputs to said first multiplexing means, and
- interconnecting means for directly connecting said I/O pad to at least one logic block without passing through said latch means and said first multiplexing means for fast input of selected signals from an external source with said external source directly driving said at least one of logic block.
An input/output (I/O) cell for interconnecting an I/O pad with internal circuitry in a programmable logic device (PLD) comprising
- a first multiplexing means having an input and a plurality of outputs, said first multiplexing means selectively connecting said input through one of said outputs to an array of logic array blocks through an internal bus of said PLD,
- latch means driven by a clock and coupled to said I/O pad and to said first multiplexing means for providing a clocked output to said I/O pad and clocked inputs to said first multiplexing means,
- a second multiplexing means having a plurality of inputs and an output for selectively connecting said I/O pad and said latch means to said input of said first multiplexing means,
- third multiplexing means having a plurality of inputs and an output for selectively connecting said I/O pad and an output of said first multiplexing means to said latch means,
- fourth multiplexing means having a plurality of inputs and an output for selectively connecting said latch means and said first multiplexing means to said I/O pad, and
- means for directly connecting said I/O pad to selected logic array blocks without passing through said latch means and said first multiplexing means.
An input/output (I/O) cell for interconnecting an I/O pad with internal circuitry in a programmable logic device (PLD) comprising
- a first multiplexing means having an input and a plurality of outputs, said first multiplexing means selectively connecting said input through one of said outputs to an array of logic array blocks through an internal bus of said PLD,
- latch means driven by a clock and coupled to said I/O pad and to said first multiplexing means for providing a clocked output to said I/O pad and clocked inputs to said first multiplexing means, and
- means for directly connecting said I/O pad to selected logic array blocks without passing through said latch means and said first multiplexing means including at least one fuse link for partitioning said means for directly connecting said I/O pad into segments thereby reducing resistance and capacitance if all segments are not used.
Dependencies are inferred from the claim text.