Integrated circuit having reduced electromagnetic emissions an integrated circuit including a variable impedance for reduced electromagnetic emission

In an integrated circuit having a power supply (VCC) and a ground (GND) buss for supplying voltage and current to the nucleus logic elements of the integrated circuit, a circuit for reducing electromagnetic emissions comprising:

• a first clock delay circuit for receiving a first clock signal at its input and for generating at its output a second clock signal delayed relative to said first clock signal;
• a second clock delay circuit adapted for receiving said second clock signal at its input and for generating at its output a third clock signal delayed relative to said second clock;
• means for comparing the phase difference between said first and third clocks and generating a control signal having a duration related to time difference between corresponding transition of said first clock signal and said third clock signal and a second control pulse having a duration determined by a second corresponding transitions of said first clock signal and said third clock signal;
• a current clamp circuit means coupled between the power supply buss and the nucleus logic and adapted to connect a resistor in series between said nucleus logic elements and said supply busses for damping supply current transient.

In an integrated circuit comprising:

• an input for receiving a clock input signal and a clock delay buffer for generating a second clock signal delayed relative to said clock input signal;
• a plurality of logic elements adapted to switch from one logic state to another logic state in response to said second clock signal;
• a first power supply buss for receiving power from an external power supply and transmitting voltage and current to said logic elements;
• a plurality of output buffers adapted to switch from one logic state to another logic state in response to data provided by said plurality of logic elements;
• a level shifter for interfacing between said nucleus logic and said output buffers;
• a second power buss for receiving power from an external power supply and transmitting voltage and current to said output buffers and said level shifter;
• and
• a circuit for reducing electromagnetic emissions generated by said integrated circuit comprising:
• a variable impedance circuit connected to series between said external power supply and said first power supply buss for providing a supply current to said first supply buss through said variable impedance circuit;
• said impedance circuit having a control input and adapted to provide a first and second impedance in response to a signal on said control input;
• and
• circuit means for providing said control input signal to increase the impedance between said first power buss and said external power supply in response to a transition of said clock input signal for a duration of time sufficient to ensure the switching of said logic elements in response to a transition of said second clock signal so as to limit the amplitude and the high frequency components of a transient voltage or current pulse supplied by said power supply in response to the switching of said logic elements and to increase the duration of said voltage or current pulse;
• said circuit means further adapted to decrease the 5 impedance between said first power buss and said external power buss when said logic elements are substantially quiescent.

A semiconductor integrated circuit device operated from an external power supply and using a clock signal, comprising:

• a plurality of semiconductor structures composing a chip nucleus, said chip nucleus including a first power input and a plurality of switching devices dissipating an initial transient switching current responsive to receipt of a first clock signal;
• a power supply pad for communicating a supply current from the external power supply to said power input of said chip nucleus;
• and
• a choke device having a second power input coupled to said power supply pad, a power output coupled to said first power input, and a variable impedance, wherein said supply current flows through said variable impedance from said second power input to said power output responsive to a second clock signal that precedes said first clock signal, and wherein said choke device impedes said supply currewnt prior to an assertion of said first clock signal.

A method for reducing electromagnetic emissions form a nucleus of an integrated circuit device operated from a power supply and responsive to a switch signal to initiate a switching state of the integrated circuit that dissipates an initial transient switching current, comprising the steps of:

• delaying an input signal to produce the switch signal to the nucleus;
• increasing an impedence, responsive to the input signal, in a conductive path for a current flow from a power supply to the nucleus, wherein said current flow provides the initial transient switching current for the nucleus;
• and thereafter
• reducing gradually said impedence.

In an electronic system including a power supply, a clock signal generator and a semiconductor integrated circuit, said semiconductor integrated circuit including a clock signal input terminal, nucleus logic elements, a plurality of output buffers and power busses for interconnecting said power supply to said nucleus logic elements and said output buffers comprising:

• means for selectively inserting a high impedance circuit device in series between said power supply and said nucleus logic for providing supply current to said nucleus logic through said high impedance prior to a transition of said clock signal to said nucleus logic;
• said means adapted to remove said high impedance circuit from in series between external power supply and said nucleus logic in a gradual manner;
• means for providing transient switching current to said nucleus logic;
• and
• output buffer circuit means for limiting transient current pulses from said external power supply and for providing initial source or sink transient current to or from a load capacitor during transitions between logic states of said output buffer.

A semiconductor integrated circuit device including a clock signal input terminal for receiving a clock signal, nucleus logic elements and terminals for connection to an external power supply comprising:

• means for selectively inserting a high impedance circuit device in series between said power supply and said nucleus logic for providing supply current to said nucleus logic through said high impedance prior to a transition of said clock signal to said nucleus logic;
• said means adapted to remove said high impedance circuit from in series between external power supply and said nucleus logic in a gradual manner;
• means for providing transient switching current to said nucleus logic;
• and
• output buffer circuit means for limiting transient current pulses from said external power supply and for providing initial source or sink transient current to or from a load capacitor during transitions between logic states of said output buffer.