Mitigating the adverse effects of charge sharing in dynamic logic circuits

A method for mitigating the adverse effects of charge sharing in a dynamic logic gate having an inverting buffer means for providing a gate output, an arming means for precharging the inverting buffer input of said inverting buffer means, and a logic means for receiving a gate input and for discharging said inverting buffer input to ground, said logic means having a plurality of field effect transistors connected in ladder-like manner, the method comprising the steps of:

• implementing said inverting buffer means by employing a CMOSFET inverter having a PMOSFET with a PMOSFET width and an NMOSFET with an NMOSFET width;
• producing the CMOSFET inverter with said PMOSFET width greater than said NMOSFET width so that said gate output switches faster from a first logic state to a second logic state than from said second logic state to said first logic state;
• disposing a precharging mechanism at a node in said logic means where logic signal paths directed to ground converge;
• and
• connecting said precharging mechanism within said dynamic logic gate so that said node is precharged when said inverting buffer input is precharged by said arming means.

A method for mitigating the adverse effects of charge sharing in a dynamic logic gate having an inverting buffer means for providing a gate output, an arming means for precharging the inverting buffer input of said inverting buffer means, and a logic means for receiving a gate input and for discharging said inverting buffer input to ground, said logic means having a plurality of field effect transistors connected in ladder-like manner, the method comprising the steps of:

• implementing said inverting buffer means by employing a CMOSFET inverter having a PMOSFET with a PMOSFET width and an NMOSFET with an NMOSFET width;
• producing said CMOSFET inverter with said PMOSFET width greater than said NMOSFET width so that said gate output switches faster from a first logic state to a second logic state than from said second logic state to said first logic state;
• and
• connecting only mutually exclusive logic signal paths to ground within said logic means.

A system for mitigating the adverse effects of charge sharing in dynamic logic gates, the system comprising:

• an inverting buffer means for providing a gate output, said inverting buffer means comprising a CMOSFET inverter, where the PMOSFET width is greater than the NMOSFET width so that a CMOSFET inverter output switches faster from a first logic state to a second logic state than from said second logic state to said first logic state;
• an arming means for precharging an inverting buffer input of said inverting buffer means;
• logic means for receiving a gate input and for discharging said inverting buffer input to ground, said logic means having a plurality of transistors connected in ladder-like manner and having logic signal paths to ground which converge at a node;
• and
• a precharging means for precharging said node when said inverting buffer input is precharged by said arming means.

A system for mitigating the adverse effects of charge sharing in dynamic logic gates, the system comprising:

• an inverting buffer means for providing a gate output, said inverting buffer means comprising a CMOSFET inverter where the PMOSFET width is greater than the NMOSFET width so that the CMOSFET inverter output switches faster from a first logic state to a second logic state than from said second logic state to said first logic state;
• an arming means for precharging an inverting buffer input of said inverting buffer means;
• and
• logic means for receiving a gate input and for discharging said inverting buffer input to ground, said logic means having a plurality of transistors connected in ladder-like manner only, thereby defining a plurality of mutually exclusive paths to ground.

A system for mitigating the adverse effects of charge sharing in dynamic logic gates, the system comprising:

• an inverting buffer means for providing a gate output, said inverting buffer means comprising a CMOSFET inverter, said CMOSFET inverter having a PMOSFET with a PMOSFET width and an NMOSFET with an NMOSFET width, said PMOSFET width being greater than said NMOSFET width so that said gate output switches faster from a first logic state to a second logic state than from said second logic state to said first logic state;
• an arming means for precharging an inverting buffer input of said inverting buffer means;
• logic means for receiving a gate input and for discharging said inverting buffer input to ground, said logic means having a plurality of transistors connected in ladder-like manner and having logic signal paths to ground which converge at a node;
• and
• a precharging means for precharging said node when said inverting buffer input is precharged by said arming means, said precharging means being connected to a common substrate shared by at least three converging transistors which converge at said node, said common substrate separating gates of said at least three transistors so that each gate is adjacent to two other gates of the remaining transistors of said at least three transistors.

A logic gate for a self-timed monotonic logic progression utilizing vector logic variables, each vector logic variable defined by vector components on respective logic paths, each vector logic variable exhibiting either an invalid state or a unique one of a plurality of possible valid states at an instant in time, said invalid state exhibited when all of said logic paths exhibit a logic low, each of said valid states exhibited when a subset of said logic paths exhibit a logic high, the logic gate for deriving an output vector from input vectors, the logic gate for mitigating the adverse effects of charge sharing by manipulating the physical layout of transistors, comprising:

• logic means comprising a plurality of ladder logic mechanisms, said logic mechanisms for receiving said input vectors, for performing logic functions upon said input vectors, and for providing a ladder logic output at a ladder logic;
• buffer means comprising a plurality of inverting buffer mechanisms associated respectively with said ladder logic mechanisms, said inverting buffer mechanisms configured to output corresponding vector components defining said output vector, said inverting buffer means for maintaining said vector components at a logic low before receiving said ladder logic outputs so that said output vector exhibits said invalid state, one of said inverting buffer mechanisms configured to receive said vector logic output and invert said ladder logic output to thereby derive said output vector in said valid state;
• arming means comprising a plurality of arming mechanisms associated respectively with said inverting buffer mechanisms, said arming mechanisms configured to periodically precharge said inverting buffer mechanisms respectively to thereby cause said inverting buffer mechanisms to maintain said vector components at said logic low;
• and
• said logic means having at least three transistors situated on a substrate with a common interstitial space separating their gates so that each gate is adjacent to two other gates of the remaining transistors.