Sample-and-hold circuit

A sample-and-hold circuit, comprising:

• a plurality of inputs for receiving input signals with instantaneous voltages;
• a plurality of capacitors;
• a plurality of analog switches connected respectively between the inputs for receiving input signals and the capacitors to charge the capacitors to the instantaneous voltages of input signals when the corresponding analog switches are conducting by a sampling signal;
• an output circuit comprising a differential amplifier and a buffer amplifier connected in cascade;
• the differential amplifier comprising a plurality of input circuit legs connected in parallel, each input circuit leg including an input transistor and a switching transistor connected in series;
• an input of the input transistor in each input circuit leg being a non-inverting input of the differential amplifier;
• a feedback connection provided between an inverting input of the differential amplifier and an output of the buffer amplifier constituting an output of the sample-and-hold circuit;
• a plurality of inputs of the switching transistors respectively connected to a plurality of logic circuits to turn on the switching transistors in a systematic chosen sequence in the hold mode of the analog switches, wherein each of the logic circuits is supplied with an input switching signal and the sampling signal;
• and
• the inputs of the input transistors connected to the capacitors to put the voltage across one of the capacitors to the output of the sample-and-hold circuit when the corresponding switching transistor is turned on.