Logical circuit for detecting a potential
AssigneeKabushiki Kaisha Toshiba
InventorToshinari Takayanagi
Life of this patent
Estimating the term…
Abstract
A logical circuit includes an inverter circuit for judging fluctuations of a potential at a potential detecting point, a power-source potential step-down circuit for supplying a potential between a potential at a switching point of the inverter circuit and a high-level power-source potential, from an output end thereof, a MOS transistor of P-channel for controlling in conductivity a location between the output end of the power-source potential step-down circuit and the potential detecting point, and a group of MOS transistors of N-channel for controlling in conductivity a location between the potential detecting point and a ground power source in accordance with an input signal.
Claims14
A logic circuit for detecting a potential change at a potential detecting point, the logic circuit comprising:
- output means, connected between a first power source potential and a second power source potential lower than said first power source potential, for comparing a potential at said potential detecting point and a potential at a switching point thereof with each other to judge fluctuations of the potential at said potential detecting point;
- voltage supply means for supplying a third potential between the potential at said switching point of said output means and said first power source potential, from an output end thereof;
- a first FET (field effect transistor) of a first conductivity type for controlling an electrical conductivity between the output end of said voltage supply means and said potential detecting point;
- and
- switch means for controlling an electrical conductivity between said potential detecting point and said second power source potential in accordance with an input signal.
A potential change detection circuit for precharging a node and then detecting a potential change of the precharged node, the circuit comprising:
- precharging means for precharging said node to a predetermined precharge level;
- and
- a logic circuit provided with a first field effect transistor connected between a high voltage level and an output terminal and having a gate terminal connected with said node, and a second field effect transistor connected between a low voltage level and said output terminal and having a gate terminal connected with said node, wherein said first and second field effect transistors have channel types that are opposite to each other, and said precharge level is selected to be a predetermined level displaced from one of said high and low voltage levels toward the other of said voltage levels by an amount within a range corresponding to twice a threshold value of one of said first and second field effect transistors.
Dependencies are inferred from the claim text.