Device and method for improving current carrying capability in a semiconductor device
AssigneeHarris Corporation
InventorChristopher L. Rexer
Life of this patent
Estimating the term…
Abstract
Semiconductor devices with elongated well regions in a stripe geometry pattern include uniformly sized source exclude areas that are longitudinally offset with respect to source exclude areas in adjacent well regions. The uniformity of the current density in neck regions is increased, thereby increasing the current carrying capability of the device.
Claims22
A semiconductor device comprising:
- a wafer of a first conductivity type with a plurality of elongated well regions of a second conductivity type therein spaced apart by neck regions of said first conductivity type,
- each of said well regions having an elongated source region of said first conductivity type along the length thereof, said source region excluding a plurality of uniformly sized, centrally located source exclude areas spaced longitudinally along the length thereof,
- said source exclude areas of adjacent ones of said well regions being offset longitudinally with respect to each other to thereby increase the uniformity of current density in said neck regions.
A semiconductor device comprising a wafer of a first semiconductor type having plural spaced-apart striped well regions of a second semiconductor type each with plural source contact areas therein that are separated from one another by source regions of the first semiconductor type, wherein said plural source contact areas of adjacent ones of said plural striped well regions are offset with respect to each other.
In a semiconductor device having a wafer of a first conductivity type with a plurality of elongated parallel well regions of the opposite conductivity type therein so that adjacent ones of said well regions are separated by a neck region of said wafer, where each of said well regions has an elongated source region of said first conductivity type extending longitudinally thereof, said source region excluding a plurality of uniformly sized, centrally located, longitudinally spaced source exclude areas, the method of enhancing the current carrying capacity of the device by increasing the uniformity of current density in said neck regions by offsetting said source exclude areas in adjacent ones of said well regions.
In a semiconductor device having a wafer of a first semiconductor type with plural spaced-apart striped well regions of a second semiconductor type therein, each of the well regions having plural source exclude areas therein separated from one another by source regions of the first semiconductor type, the method of decreasing the on-resistance of the semiconductor device comprising the steps of offsetting the location of the source exclude areas in adjacent ones of the well regions.
The method of increasing the current carrying capacity of a semiconductor device having a plurality of spaced stripes of a first semiconductor type each having plural source contact areas therein separated from each other by source regions of a second semiconductor type, comprising the step of offsetting said source contact areas in adjacent ones of said stripes to increase the uniformity of the density of the current in space between said stripes.
Dependencies are inferred from the claim text.