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US 5,317,180 AGranted
Vertical DMOS transistor built in an n-well MOS-based BiCMOS process
AssigneeTexas Instruments Incorporated
InventorsLouis N. Hutter, John P. Erdeljac
Life of this patent
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AssigneeTexas Instruments Incorporated
InventorsLouis N. Hutter, John P. Erdeljac
Estimating the term…
An integrated circuit is provided wherein bipolar, CMOS and DMOS devices are merged together on one chip with fabrication taking place from a CMOS point of view rather than from a bipolar point of view as in the prior art and p-type epitaxial silicon is used as opposed to n-type epitaxial silicon in the prior art. The integrated circuit uses a P+ substrate upon which a P- epitaxial layer is formed. N+ buried regions isolate the DMOS, PMOS and NPN bipolar devices from the P-epitaxial layer. Each of the devices is formed in a N-well with a first level of polysilicon gate layer providing both the gate and masking for the backgate diffusion of the DMOS device and a sidewall oxide later formed on the first level gate layer to control the diffusion of the source and drain regions of the DMOS device to control channel length. A second level of polysilicon layer provides the gate structures for the CMOS devices as well as one plate of a capacitor. The second level of polysilicon acts as a mask for the source and drain region implants of the CMOS devices. A sidewall oxide later formed on the second polysilicon level further controls the channel lengths of the CMOS structures. A third level of polysilicon provides the second capacitor plate for the capacitor. The DMOS device is isolated from the remaining circuitry by the p-type epitaxial layer and the peripheral portion of the DMOS device is terminated by a PN junction, thereby avoiding the necessity of having a tapered field oxide.
An integrated circuit having plural active components including a DMOS transistor and a bipolar transistor, comprising:
An integrated circuit having plural active components including a DMOS transistor and a bipolar transistor, comprising:
An integrated circuit having each of PMOS, NMOS, DMOS and bipolar transistors, said bipolar transistor having a collector region, each of said transistors having a current path, comprising:
Dependencies are inferred from the claim text.