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US 5,317,178 AGranted
Offset dual gate thin film field effect transistor
AssigneeIndustrial Technology Research Institute
InventorNeng-Wei Wu
Life of this patent
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Abstract
A field effect transistor having a thin polycrystalline silicon layer as a channel region, a lower gate electrode beneath the silicon layer, and upper gate electrode with an offset above the silicon layer, and a gate dielectric layer between the lower gate electrode and the silicon layer, and a gate dielectric layer between the upper gate electrode and the silicon layer.
Claims8
An offset dual gate thin film field effect transistor comprising:
- an insulating substrate;
- a narrow stripe of conductive material on said substrate to serve as a lower gate electrode;
- a first thin gate dielectric layer over said lower gate electrode;
- a layer of polycrystalline silicon over said lower gate electrode and extending beyond the edges thereof;
- a second gate dielectric layer over said layer of polycrystalline silicon;
- a upper offset gate electrode located over said lower gate electrode with a portion thereof providing an offset in the range of 0.2 to 0.6 micrometers extending beyond one edge of said lower gate electrode;
- source and drain regions in said layer of polycrystalline silicon layer located beyond opposite edges of said upper offset gate electrode.
4 more elements
Dependencies are inferred from the claim text.